TIDUF35A June   2023  – October 2024 AM6442

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1  AM6442 Microprocessor
      2. 2.3.2  DP83867 gigabit Ethernet Physical Transceiver
      3. 2.3.3  DP83TD510E Single-Pair Ethernet Physical Transceiver
      4. 2.3.4  MSPM0G1107 Microcontroller
      5. 2.3.5  LMK1C1106 6-Channel Output LVCMOS 1.8V Buffer
      6. 2.3.6  LMK6C Low-Jitter, High-Performance, Bulk-Acoustic-Wave (BAW) Fixed-Frequency LVCMOS Oscillator
      7. 2.3.7  TLVM13630 High-Density, 3V to 36V Input, 1V to 6V Output, 3A Step-Down Power Module
      8. 2.3.8  LM74700-Q1 Reverse-Polarity Protection Ideal Diode
      9. 2.3.9  TPS62825A Synchronous Step-Down DC-DC Converter
      10. 2.3.10 LMR36006 Ultra-Small Synchronous Step-Down Converter
      11. 2.3.11 TLV62568A High-Efficiency Step-Down Buck Converter With Forced PWM
  9. 3System Design Theory
    1. 3.1 Power Subsystem
    2. 3.2 AM6442 System on Module Subsystem
    3. 3.3 Ethernet Subsystem
    4. 3.4 Power Over Data Line (PoDL) Subsystem
    5. 3.5 Additional Subsystems
      1. 3.5.1 USB 3.1 Interface
      2. 3.5.2 Micro SD Card Interface
      3. 3.5.3 SimpleLink CC3301 Wi-Fi 6 and Bluetooth Low-Energy BoosterPack Interface
      4. 3.5.4 AM6442 UART Interface
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Board Interface
        1. 4.1.1.1 Boot Switch Configuration
        2. 4.1.1.2 Starting up the Reference Design
    2. 4.2 Software Requirements
      1. 4.2.1 PoDL PSE Protocol Programming
      2. 4.2.2 Create an SD Card Image With U-Boot and Linux
    3. 4.3 Test Setup and Procedure
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author
  13. 7Revision History

3.3 Ethernet Subsystem

There are two Ethernet subsystems in this reference design. One subsystem consisting of four DP83TD510E Ethernet PHYs, supporting single-pair Ethernet. The second subsystem with one DP83867 device supports gigabit Ethernet for cloud connection, see Figure 3-5.

TIDA-010262 Ethernet Subsystem and Clocking on Gateway BoardFigure 3-5 Ethernet Subsystem and Clocking on Gateway Board

The MAC-to-Ethernet PHY connection for all five PHYs is RGMII. RGMII can be used for 1000Mbps speed as well as for 10Mbps speed. The MAC enables the appropriate speed on the RGMII clock line towards the Ethernet PHY.

The five MACs are integrated into the AM6442 microprocessor. Four of the five MACs are within the industrial communication subsystem (ICSS) peripheral. The fifth MAC port is within the CPSW peripheral. All MACs are accessible as network interfaces in the Linux operating system.

The DP83867 Gbit Ethernet PHY is configured for the MDIO address 1. The RGMII interface is connected to the CPSW peripheral of the AM6442 processor. The DP83867 is also connected to the MDIO, MDC interface of the CPSW. The Gbit Ethernet port uses a standard RJ45 Ethernet connector. The two LEDs inside the RJ45 connector show the link-up and receive or transmission activity state of the PHY.

The DP83TD510E PHYs are configured to use MDIO address 0 and 1. Two of the four Ethernet PHYs are connected to ICSS0 and the second two devices are connected to ICSS1. The MDIO, MDC lines of each of the two PHYs are connected to the appropriate ICSS0 or ICSS1 peripheral. For the SPE ports there are two connector options available in parallel: Phoenix Contact SPE-T1 connector or standard screw terminal from Wurth Electronics. Each SPE port has three LEDs to indicate PHY states link (short reach and long reach) and receive or transmit activity.

Within the MDI path of the PHYs, PoDL is coupled onto the MDI path.

The 25MHz clock source is generated by the 25MHZ BAW oscillator LMK6CE. This 25MHz clock is fed into the LMK1C1106 LMCMOS clock buffer with up to 6 outputs. The 25MHz outputs are connected to the five Ethernet PHYs.