TIDUF68A February   2024  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG2100
      2. 2.3.2 INA241A
      3. 2.3.3 AMC0106M05
      4. 2.3.4 LMR38010
  9. 3System Design Theory
    1. 3.1 Three-Phase GaN Inverter Power Stage
      1. 3.1.1 LMG2100 GaN Half-Bridge Power Stage
    2. 3.2 Inline Shunt Precision Phase-Current Sensing
      1. 3.2.1 INA241A Ultra-Precise Current Sense Amplifier with Enhanced PWM Rejection
      2. 3.2.2 AMC0106M05 Precision, ±50mV Input, Functionally Isolated, Delta-Sigma Modulator
    3. 3.3 Phase Voltage and DC Input Voltage Sensing
    4. 3.4 Power-Stage PCB Temperature Monitor
    5. 3.5 Power Management
      1. 3.5.1 48V to 5V DC/DC Converter
      2. 3.5.2 5V to 3.3V Rail
    6. 3.6 Interface to Host MCU
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 TIDA-010936 PCB Overview
      2. 4.1.2 TIDA-010936 Jumper Settings
      3. 4.1.3 Interface to C2000™ MCU LaunchPad™ Development Kit
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Power Management and System Power Up and Power Down
      2. 4.4.2 GaN Inverter Half-Bridge Module Switch Node Voltage
        1. 4.4.2.1 Switch Node Voltage Transient Response at 48V DC Bus
          1. 4.4.2.1.1 Output Current at ±1A
          2. 4.4.2.1.2 Output Current at ±10A
        2. 4.4.2.2 Impact of PWM Frequency to DC-Bus Voltage Ripple
        3. 4.4.2.3 Efficiency Measurements
        4. 4.4.2.4 Thermal Analysis
        5. 4.4.2.5 No Load Loss Test (COSS Losses)
      3. 4.4.3 Phase-Current Sensing
  11. 5Design and Documentation Support
    1. 5.1 Design Files [Required Topic]
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 Layout Prints
      4. 5.1.4 Altium Project
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Recognition
  14. 8Revision History

3.1.1 LMG2100 GaN Half-Bridge Power Stage

This design leverages three LMG2100R044 100V pulsed, 35A half-bridge power stage devices, with integrated gate-driver and enhancement-mode Gallium Nitride (GaN) FETs. The PCB space is further reduced due to high integration and the fact that only a few additional passive components are required. Figure 3-2 shows the schematic of one half-bridge.


TIDA-010936 Half-Bridge Power Stage Schematic for Phase A

Figure 3-2 Half-Bridge Power Stage Schematic for Phase A

The 48V DC-link voltage is connected to the LMG2100 VIN pin and referenced to the power ground (PGND) pin. Local ceramic bypass capacitors C21, C22, C23 (100nF) and C15, C16, C17 (1μF) are placed in parallel close between the VIN and PGND pins to minimize loop inductance.

The LMG2100 integrated gate driver is supplied with 5V. A 2.2μF and 0.1μF ceramic bypass capacitor (C14, C20) are placed close to the VCC pin and AGND pin, as suggested in the data sheet.

Sequencing is not required for the 5V at VCC and the 48V at VIN, neither during the power up or power down of the input DC voltage.

Two 100nF ceramic bootstrap capacitors (C26 and C27) are placed close to the HB (high-side gate-driver bootstrap rail) and HS (high-side GaN-FET source connection) pins. R5 and R7 are placed to configure the slew rate of the switch node rising edge and related turn-on time. The R5 resistor in the VCC path can limit the turn-on slew rate of the low-side GaN-FET and the R7 resistor in the bootstrap path is for high-side GaN-FET. The R5 and R7 resistors for the tests are 3Ω.

The complementary PWM signals for the high-side and low-side switch from the PWM buffer are low-pass filtered with R9, C29 and R11, C31 to reject high-frequency impulse noise and avoid false switching with a cutoff frequency of around 160MHz and a propagation of around 1ns. The SW (switch node) pin is connected to the motor phase A terminal through a series inline shunt for phase-current sensing, and respectively for the other LMG2100R044 half-bridges to the phase B and the phase C terminal.