TIDUF82B August   2024  – May 2025 DRV8162 , INA241A , ISOM8710

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Reference Design Overview
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Hardware Design
        1. 2.2.1.1 Power Stage Gate Driver
          1. 2.2.1.1.1 Gate Driver
          2. 2.2.1.1.2 Protection Features
          3. 2.2.1.1.3 VGVDD Definition
          4. 2.2.1.1.4 Strap Functions
        2. 2.2.1.2 Power Stage FETs
          1. 2.2.1.2.1 VGS versus RDS(ON)
        3. 2.2.1.3 Phase Current and Voltage Sensing
          1. 2.2.1.3.1 Phase A and Phase B Current Sensing
          2. 2.2.1.3.2 Phase C Current Sensing
          3. 2.2.1.3.3 Voltage Sensing
        4. 2.2.1.4 Host Processor Interface
        5. 2.2.1.5 Gate Drive Shutdown Path
        6. 2.2.1.6 System Diagnostic Measurements
          1. 2.2.1.6.1 Temperature Measurement
        7. 2.2.1.7 System Power Supply
          1. 2.2.1.7.1 12V Rail
          2. 2.2.1.7.2 3.3V Rail
      2. 2.2.2 Software Design
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8162L
      2. 2.3.2 INA241A
      3. 2.3.3 AMC0106M05
      4. 2.3.4 TPSM861253
      5. 2.3.5 LMR38010
      6. 2.3.6 TMP6131
      7. 2.3.7 ISOM8710
  9. 3Hardware, Software Test Requirements and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 PCB Overview
      2. 3.1.2 Hardware Configuration
        1. 3.1.2.1 Prerequisites
        2. 3.1.2.2 Default Resistor and Jumper Configuration
        3. 3.1.2.3 Connector
          1. 3.1.2.3.1 Host Processor Interface
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Power Management
        1. 3.3.1.1 Power Up
        2. 3.3.1.2 Power Down
      2. 3.3.2 Gate Voltage and Phase Voltage
        1. 3.3.2.1 20 VDC
        2. 3.3.2.2 48 VDC
        3. 3.3.2.3 60 VDC
      3. 3.3.3 Digital PWM and Gate Voltage
      4. 3.3.4 Phase-Current Measurements
      5. 3.3.5 System Test Results
        1. 3.3.5.1 Thermal Analysis
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors
  12. 6Revision History

3.3.3 Digital PWM and Gate Voltage

In these tests, the propagation delay between the PWM signal and the MOSFET gate voltage is measured in a low-side channel first; and then the dead time between the high-side and low-side digital PWMs as well as the gate voltages of the MOSFETs are measured. Figure 3-19 shows the test setup.

TIDA-010956 Test Setup for the Digital PWM and Gate Voltage Measurements Figure 3-19 Test Setup for the Digital PWM and Gate Voltage Measurements

The system uses a 48V VIN in these tests and the motor is set to a fixed angle with open loop control. The signals are measured in Phase C and all signals are referenced to GND.

The propagation delay in turn-on and turn-off appear in Figure 3-20 and Figure 3-21.

TIDA-010956 Propagation Delay in Turn-OnFigure 3-20 Propagation Delay in Turn-On
TIDA-010956 Propagation Delay in Turn-offFigure 3-21 Propagation Delay in Turn-off

The turn-on delay is measured at about 200ns and the turn-off delay is measured at about 70ns. The turn-on is postponed by about 130ns due to an extra dead time that is introduced with the DRV8162L, following the DT pin setting of a 3.3kΩ RDT connecting to GND.

Figure 3-22 and Figure 3-23 show the 200ns dead time of the PWM signals and the corresponding gate voltages when the half bridge is switching from low to high (CH2 for CL and CH3 for CH).

TIDA-010956 PWM Inputs in Positive Shift, DT = 200nsFigure 3-22 PWM Inputs in Positive Shift, DT = 200ns
TIDA-010956 Gate Voltages in Positive Shift, DT = 343nsFigure 3-23 Gate Voltages in Positive Shift, DT = 343ns

The dead time between the high-side and the low-side gate voltages is expanded to about 340ns with the DRV8162L.

Figure 3-24 and Figure 3-25 show the half bridge is switching from high to low. The dead time is also expanded to about 340ns with the RDT setting.

TIDA-010956 PWM Inputs in Negative Shift,DT = 200nsFigure 3-24 PWM Inputs in Negative Shift,
DT = 200ns
TIDA-010956 Gate Voltages in Negative Shift,DT = 338nsFigure 3-25 Gate Voltages in Negative Shift,
DT = 338ns

This DRV8162L automatically inserts dead time and can vary between 20ns to 370ns, depending on the RDT value. See the data sheet for the details.