The schematic shown in Figure 3-11 can be synchronized to an external clock signal only if the duty cycle of the latter is larger than the duty cycle of the controller (larger than 93%). This design can be synchronized to an external clock with 50% duty cycle by implementing the design shown in Figure 3-18. The various point-of-load supplies can be synchronized to the external clock which is available on the power connector discussed in Section 3.5. The signal from the clock source pin DC_DC_CLK_1 is further is divided and distributed to respective supplies and the switching frequencies. Figure 3-18 shows the schematic of the implementation. The source clock is first given as an input to the 9-channel integrated clock buffer and divider device CDCE949. The eight outputs are 500kHz for the seven TPS54218 buck devices and one TPS61178 for the 5V rail, the 9th output is 250kHz for the high-voltage circuit. The configuration of the device CDCE949 can be stored in the integrated EEPROM CDCEL9XXPROGEVM or over the I²C bus. If CDCEL9XXPROGEVM is used, the configuration file is found in the design files.

Figure 3-18 External Clock Synchronization Implementation Schematic

The high-voltage circuit can be synchronized to an external clock with 50% duty cycle. The boost regulator (LM5158) imposes a limit on the duty cycle clock pulse width to be larger than the duty cycle of the supply which is very high in the current implementation. Figure 3-18 shows the schematic of the implementation.