SNAS687C June   2016  – November 2017 LMK60A0-148351 , LMK60A0-148M , LMK60E0-156257 , LMK60E2-150M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIA|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Low Noise, High Performance
    • Jitter: 150 fs RMS typical Fout > 100 MHz
    • PSRR: –60 dBc, Robust Supply Noise Immunity
  • Supported Output Format
    • LVPECL and LVDS up to 800 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±50 ppm (LMK60X2) and ±25 ppm (LMK60X0)
  • 3.3-V Operating Voltage
  • Industrial Temperature Range (–40ºC to +85ºC)
  • 7-mm × 5-mm 6-pin Package That is Pin-Compatible With Industry Standard 7050 XO Package

2 Applications

  • High-Performance Replacement for Crystal-, SAW-, or Silicon-based Oscillators
  • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
  • Test and Measurement
  • Medical Imaging
  • FPGA, Processor Attach

3 Description

The LMK60XX device is a low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL, and LVDS up to 800 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ±5% supply.

Device Information(1)

PART NUMBER OUTPUT FREQ (MHz) AND FORMAT TOTAL FREQ STABILITY (ppm) PACKAGE / SIZE
LMK60E2-150M 150 LVPECL ±50 6-pin QFM,
7 mm × 5 mm
LMK60E0-156257 156.257 LVPECL ±25
LMK60A0-148351 148 + 32/91 LVDS ±25
LMK60A0-148M 148.5 LVDS ±25
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout