SLUSD38 November   2016 TPS53659


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  2. 2Revision History
  3. 3Device and Documentation Support
    1. 3.1 Receiving Notification of Documentation Updates
    2. 3.2 Community Resources
    3. 3.3 Trademarks
    4. 3.4 Electrostatic Discharge Caution
    5. 3.5 Glossary
  4. 4Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview


  • Full VR13 Server Feature Set Including Digital Input Power Monitor
  • Programmable Loop Compensations
  • Configurable with Non-Volatile Memory (NVM) for Low External Component Counts
  • Individual Phase Current Calibrations and Reports
  • Dynamic Phase Shedding with Programmable Current Threshold for Optimizing Efficiency at Light and Heavy Loads
  • Fast Phase-Adding for Undershoot Reduction (USR)
  • Backward VR12.0 and VR12.5 Compatible
  • 8-Bit DAC with Selectable 5 mV or 10 mV Resolution and Output Ranges from 0.25 V to 1.52 V or 0.5 V to 2.8125 V for Dual Channels
  • Driverless Configuration for Efficient High-Frequency Switching
  • Fully Compatible with TI NextFET™ Power Stage for High-Density Solutions
  • Accurate, Adjustable Voltage Positioning
  • Frequency Selections with Closed-loop Frequency Control: 300 kHz to 1 MHz
  • Patented AutoBalance™ Phase Balancing
  • Selectable, 16-level Per-Phase Current Limit
  • PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
  • Dynamic Output Voltage Transitions with Programmable Slew Rates via SVID or PMBus Interface
  • Conversion Voltage Range: 4.5 V to 17 V
  • Low Quiescent Current
  • 5 mm × 5 mm, 40-Pin, WQFN PowerPad™ Package


  • VR13 Memory Power of Server and Telecom Applications
  • ASIC Needs Dual Power Rails
  • High-Performance Processor Power


The TPS53659 is a fully VR13 SVID compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCORE slew rate and voltage positioning round out the Intel® features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS53659 device if offered in a thermally enhanced 40-pin WQFN packaged and is rated to operate from –40°C to 125°C.

Table 1-1 Device Information(1)

TPS53659 WQFN (40) 5 mm × 5 mm
For more information, see, Mechanical, Packaging, and Orderable Information.