SLVSBO3A December   2013  – December 2015 TPS657120

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: General Functions
    6. 4.6  Electrical Characteristics: DCDC1 and DCDC2
    7. 4.7  Electrical Characteristics: DCDC3
    8. 4.8  Electrical Characteristics: RF-LDOs
    9. 4.9  Electrical Characteristics: Digital Inputs, Digital Outputs
    10. 4.10 Electrical Characteristics: Thermal Shutdown, Undervoltage Lockout
    11. 4.11 Electrical Characteristics: RFFE Timing Parameters
    12. 4.12 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Default Settings
      2. 5.3.2  Linear Regulators
        1. 5.3.2.1 Low Quiescent Current (Eco) Mode
        2. 5.3.2.2 Output Discharge
        3. 5.3.2.3 LDO Enable
        4. 5.3.2.4 LDO Voltage Range
        5. 5.3.2.5 LDO Power Good Comparator
      3. 5.3.3  Step-down Converters DCDC1 and DCDC2
      4. 5.3.4  Power Save Mode
      5. 5.3.5  Dynamic Voltage Positioning (Optional)
      6. 5.3.6  Soft Start / Enable
      7. 5.3.7  Dynamic Voltage Scaling (DVS) for DCDC1, DCDC2 and DCDC3
      8. 5.3.8  100% Duty Cycle Low Dropout Operation
      9. 5.3.9  180° Out-of-Phase Operation
      10. 5.3.10 Undervoltage Lockout for DCDC1, DCDC2, DCDC3, LDO1 and LDO2
      11. 5.3.11 Output Voltage Discharge
      12. 5.3.12 Short-Circuit Protection
      13. 5.3.13 Output Voltage Monitoring
      14. 5.3.14 Step-Down Converter and LDO Enable; pins CLK_REQ1 and CLK_REQ2
      15. 5.3.15 Step-Down Converter DCDC3
      16. 5.3.16 DCDC3_SEL Control
        1. 5.3.16.1 DCDC3_SEL Control - Voltage Mapping Option
        2. 5.3.16.2 DCDC3_SEL Control - Mapping the Enable Signal for the Negative Current Limit of DCDC3 to DCDC3_SEL; Additional Option for Rev 1.1 and Higher Only
      17. 5.3.17 Bypass Switch
      18. 5.3.18 DCDC3 Output Voltage Ramp Support
      19. 5.3.19 VCON Decoder
      20. 5.3.20 Thermal Monitoring and Shutdown
      21. 5.3.21 GPIOs
      22. 5.3.22 nRESET Input ; ADR_SELECT Input
      23. 5.3.23 Power State Machine
      24. 5.3.24 Implementation of Internal Power-Up and Power-Down Sequencing
      25. 5.3.25 VDDIO Voltage for Push-pull Output Stages / Interface
      26. 5.3.26 TPS657120 On Off Operation
        1. 5.3.26.1 TPS657120 Power-Up
        2. 5.3.26.2 TPS657120 PWR_REQ Driving DCDC1, DCDC2 and LDO1
      27. 5.3.27 MIPI RFFE Interface
        1. 5.3.27.1 MIPI RFFE Write Cycle
        2. 5.3.27.2 MIPI RFFE Read Cycle
    4. 5.4 Device Functional Modes
    5. 5.5 Register Maps
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 6.2.2.1.1 Inductor Selection
          2. 6.2.2.1.2 Output Capacitor Selection
          3. 6.2.2.1.3 Input Capacitor / Output Capacitor Selection
          4. 6.2.2.1.4 Voltage Change on DCDC1, DCDC2 and DCDC3
      3. 6.2.3 Application Curve
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • 3 Step-Down Converters:
    • VIN Range From 2.8 V to 5.5 V
    • Power Save Mode at Light Load Current
    • Output Voltage Accuracy in PWM Mode ±2%
    • Typical 16-μA Quiescent Current per DCDC1 and DCDC2 Converter
    • Typical 26-μA Quiescent Current for DCDC3 Converter
    • Dynamic Voltage Scaling
    • 100% Duty Cycle for Lowest Dropout
  • 2 LDOs:
    • 2 × 10-mA Output Current
    • Low Noise RF-LDOs
    • Output Voltage Range 1.2 V to 3.4 V
    • 32-μA Quiescent Current
    • Pre-Regulation Support by Separate Power Inputs
    • ECO mode
    • VIN Range of LDOs:
      • LDO1: 2.0 V to 5.5 V
      • LDO2: 2.8 V to 5.5 V
  • 2 GPIOs
  • Thermal Shutdown
  • Bypass Switch
    • Used with DCDC3 Powering an RF-PA
  • Interface
    • 26 MHz-MIPI RFFE Interface
  • Undervoltage Lockout
  • Flexible Power-Up and Power-Down Sequencing
  • 2.5-mm × 2.3-mm DSBGA Package with 0.4-mm Pitch

1.2 Applications

  • Data Cards
  • Smartphones

1.3 Description

The TPS657120 provides three configurable step-down converters with up to 2-A output current.This device also has 2 LDO regulators. LDO1 can be supplied from either the input voltage directly or from a pre-regulated supply such as DCDC1 or DCDC2. The input voltage to LDO2 is used as an analog supply input and therefore must be tied to the input voltage at the same voltage level with VINDCDC1/2 and VINDCDC3. The internal power-up and power-down controller is configurable and can support any power-up/power-down sequences (OTP based). All LDOs and DCDC converters are controllable by a MIPI RFFE compatible interface, by pins PWRON, CLK_REQ1 and CLK_REQ2, or both. In addition, there is a nRESET as well as a RFFE address select (ADR_SELECT) input which can alternatively be used as general purpose I/Os with a 1-mA sink capability. The TPS657120 comes in a 6-ball × 5-ball DSBGA package (2.5 mm × 2.3 mm) with a 0.4-mm pitch.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS657120 DSBGA (30) 2.31 mm × 2.51 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.

1.4 Functional Block Diagram

TPS657120 TPS65712_blockdiagram5x6.gif Figure 1-1 Functional Block Diagram