SLUSC72B May   2015  – March 2016 UCC27201A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
        1. 7.3.1.1 UVLO (Under Voltage Lockout)
        2. 7.3.1.2 Level Shift
        3. 7.3.1.3 Boot Diode
        4. 7.3.1.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
        2. 8.2.2.2 Dynamic Switching of the MOSFETs
        3. 8.2.2.3 Delay Matching and Narrow Pulse Widths
        4. 8.2.2.4 Boot Diode Performance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 140°C Ambient Operating Temperature Range
    • Device HBM Classification Level 1C
    • Device CDM Classification Level C3
  • Negative Voltage Handling on HS (–18 V)
  • Drives Two N-Channel MOSFETs in High-Side/Low-Side Configuration
  • Maximum Boot Voltage: 120 V
  • Maximum VDD Voltage: 20 V
  • On-Chip 0.65-V VF, 0.6-Ω RD Bootstrap Diode
  • Greater than 1 MHz of Operation
  • 20-ns Propagation Delay Times
  • 3-A Sink, 3-A Source Output Currents
  • 8-ns Rise and 7-ns Fall Time with 1000-pF Load
  • 1-ns Delay Matching
  • Under Voltage Lockout for High-Side and Low-Side Driver
  • Offered in 8-Pin PowerPad™ SOIC-8 (DDA) and 10-Pin VSON (DMK) Packages

2 Applications

  • Auxiliary Inverters
  • DC-to-DC Converters for Power Train
  • Switch Mode Power Supplies
  • Motor Control
  • Half-Bridge Applications and Full-Bridge Converters
  • Two-Switch Forward Converters
  • Active-Clamp Forward Converters
  • High Voltage Synchronous-Buck Converters
  • Class-D Audio Amplifiers

3 Description

The UCC27201A-Q1 high frequency N-Channel MOSFET driver includes a 120-V bootstrap diode and high-side/low-side driver with independent inputs for maximum control flexibility. This allows for N-Channel MOSFET control in half-bridge, full-bridge, two-switch forward and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 1-ns between the turn-on and turn-off of each other. The UCC27201A-Q1 is based on the popular UCC27200 and UCC27201 drivers, but offer some enhancements. In order to improve performance in noisy power supply environments the UCC27201A-Q1 has the ability to withstand a maximum of -18 V on its HS pin.

An on-chip bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold.

The UCC27201A-Q1 has TTL-compatible thresholds and is offered in a 10-Pin VSON and an 8-pin SOIC with a thermal pad.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
UCC27201A-Q1 DDA (8) 4.89 mm × 3.90 mm
DMK (10) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application Diagram

UCC27201A-Q1 sys_diagram_SLUSC72.gif

4 Revision History

Changes from A Revision (October 2015) to B Revision

  • Added 10-Pin VSON DMK Package information.Go

Changes from * Revision (May 2015) to A Revision

  • Changed the "Minimum input pulse width" value From: 50 ns Max To: 50 ns TypGo
  • Changed ILO = IHO = –100 mA condition to ILO = IHO = 100 mA Go
  • Changed ILO = IHO = 100 mA condition to ILO = IHO = –100 mA.Go