Directory Structure:

PROJECT_NAME -------> rtl
               |----> coregen
               |----> ucf
               |----> syn

"rtl"     : Contains rtl (verilog source code).
"coregen" : Contains macro for design including clocking blocks.
"ucf"     : Includes pins and constraints file.
"syn"     : This folder includes ISE project file. Generated bit, pad and timing information are stored in this directory.

Running project:
            Start ISE in "syn" folder. Open project ADC07D1520. This sould list all the files it needs for the project. Before generating bit-file, user should select both fifo modules "fifo_96_4k.xco and fifo_48X16.xco in the design source panel and in the process panel, expand Design Utilities and click on "Regenerate All Cores". This will generate required files for ISE to successfully run the project.

            After regenerating all cores, click on adc07d1520 and click "Generate Programming File" in the process window. This should generate bit-file. This process takes few minutes. Generated files are in "syn" directory.
