******************************************************************************
* *
* TEXAS INSTRUMENTS INCORPORATED
* Standard Linear and Logic Group
* HSPICE Model for SN74AUC244
* PROPERTY OF TEXAS INSTRUMENTS INCORPORATED. UNAUTHORIZED
* REPRODUCTION AND/OR DISTRIBUTION IS STRICTLY PROHIBITED.
*
* THIS PRODUCT IS PROTECTED UNDER COPYRIGHT LAW.
* CREATED 2005, (C) COPYRIGHT 2005, TEXAS INSTRUMENTS
* INCORPORATED, ALL RIGHTS RESERVED
*
* UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE
* CONTRARY, TEXAS INSTRUMENTS (TI) IS PROVIDING THE IBIS
* MODELS AND WITHOUT ANY WARRANTY, EXPRESSED OR
* IMPLIED. TI ASSUMES NO LIABILITY FOR:
* 1) THE ACCURACY OF THE HSPICE MODELS PROVIDED TO YOUR
* COMPANY;
* 2) THE PROPER FUNCTIONING OF THESE HSPICE MODELS IN YOUR
* DESIGN OR FOR ANY RESULTING APPLICATIONS; OR
* 3) INFRINGEMENT OF PATENTS, COPYRIGHTS OR INTELLECTUAL
* PROPERTY RIGHTS RESULTING FROM YOUR USE OF THESE HSPICE
* MODELS.
*
* TI PROVIDES HSPICE MODELS AS A SERVICE TO OUR CUSTOMERS.
* YOU AND YOUR COMPANY SHALL NOT DISTRIBUTE, SELL OR GIVE
* THESE MODELS TO ANYONE ELSE WITHOUT PRIOR WRITTEN
* PERMISSION FROM TI.
*
* TI RESERVES THE RIGHT TO MAKE CHANGES TO OUR PRODUCTS OR
* TO DISCONTINUE ANY SEMICONDUCTOR PRODUCT OR SERVICE
* WITHOUT NOTICE, AND ADVISES OUR CUSTOMERS TO OBTAIN THE
* LATEST VERSION OF RELEVANT INFORMATION TO VERIFY, BEFORE
* PLACING ORDERS, THAT THE INFORMATION BEING RELIED ON IS
* CURRENT.
*
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* INFORMATION PROVIDED SHALL SERVE AS ACCEPTANCE OF THESE
* TERMS AND CONDITIONS. IF YOU DO NOT ACCEPT THESE TERMS,
* YOU SHOULD RETURN OR DESTROY THE HSPICE MODELS AND ANY
* OTHER ACCOMPANYING INFORMATION IMMEDIATELY.
************************************************************************
**** HSPICE EXECUTION OPTIONS ****
************************************************************************
*
** Generated for: hspiceD
** Design cell name: sim_TOP_HSPICE

.PARAM enable=1
.PARAM sel1=1
.PARAM sel2=1
.PARAM vdda_pwr=3.6

.INCLUDE TS3DV642.inc

.PROBE TRAN
+    V(xits3dv642.vbg)
+    V(xits3dv642.vbggd)
+    V(xits3dv642.vcp_9v_7v)
+    V(vdda)
+    V(en)
+    V(sel2)
+    V(sel1)
.TRAN 1e-9 3e-3 START=0.0

.OP

.TEMP 25.0
.OPTION
+    ARTIST=2
+    IMAX=10
+    IMIN=0.1
+    INGOLD=2
+    LVLTIM=3
+    MEASOUT=1
+    METHOD=GEAR
+    PARHIER=LOCAL
+    POST_VERSION=9601
+    PSF=2
+    SCALE=1e-6

** Library name: TS3DV642_users
** Cell name: sim_TOP_HSPICE
** View name: schematic
xits3dv642 vdda a0 en sel2 sel1 0 c11 b11 c10 b9 b10 c9 c8 b8 c7 b7 c6 b6 c5 b5 c4 b4 c3 b3 c2 b2 b0 c0 c1 b1 a11 a9 a7 a5 a2 a4 a10 a8 a6 a3 a1 TS3DV642_TOP
v4 en 0 DC='enable*vdda_pwr' PWL 0 0 125e-6 0 125.0025e-6 'enable*vdda_pwr' 2.4e-3 'enable*vdda_pwr' 2.4000025e-3 0 1 0 TD=0
v0 vdda 0 DC=vdda_pwr PWL 0 0 20e-6 0 21e-6 vdda_pwr 2.5e-3 vdda_pwr 2.501e-3 0 1 0 TD=0
v3 sel2 0 DC=0 AC 0 0 PULSE 0 'sel2*vdda_pwr' 1.13e-3 2.5e-9 2.5e-9 1e-3 2e-3
v1 sel1 0 DC=0 AC 0 0 PULSE 0 'sel1*vdda_pwr' 630e-6 2.5e-9 2.5e-9 500e-6 1e-3
.END
