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//*****************************************************************************
//
// usci_uart.c - Driver for the usci_uart Module.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup usci_uart_api usci_uart
//! @{
//
//*****************************************************************************

#include "inc/hw_regaccess.h"
#include "inc/hw_memmap.h"

#ifdef __MSP430_HAS_USCI_Ax__
#include "usci_uart.h"

#include <assert.h>

bool USCI_UART_initAdvance ( uint16_t baseAddress,
    uint8_t selectClockSource,
    uint16_t clockPrescalar,
    uint8_t firstModReg,
    uint8_t secondModReg,
    uint8_t parity,
    uint8_t msborLsbFirst,
    uint8_t numberofStopBits,
    uint8_t uartMode,
    uint8_t overSampling
    )
{
    USCI_UART_initParam param = {0};
    param.selectClockSource = selectClockSource;
    param.clockPrescalar = clockPrescalar;
    param.firstModReg = firstModReg;
    param.secondModReg = secondModReg;
    param.parity = parity;
    param.msborLsbFirst = msborLsbFirst;
    param.numberofStopBits = numberofStopBits;
    param.uartMode = uartMode;
    param.overSampling = overSampling;

    return USCI_UART_init(baseAddress, &param);
}

bool USCI_UART_init(uint16_t baseAddress, USCI_UART_initParam *param)
{
    bool retVal = STATUS_SUCCESS;

    //Disable the USCI Module
    HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;

    //Clock source select
    HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCSSEL_3;
    HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource;

    //MSB, LSB select
    HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCMSB;
    HWREG8(baseAddress + OFS_UCAxCTL0) |= param->msborLsbFirst;

    //UCSPB = 0(1 stop bit) OR 1(2 stop bits)
    HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCSPB;
    HWREG8(baseAddress + OFS_UCAxCTL0) |= param->numberofStopBits;

    //Parity
    switch (param->parity){
        case USCI_UART_NO_PARITY:
            //No Parity
            HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPEN;
            break;
        case USCI_UART_ODD_PARITY:
            //Odd Parity
            HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;
            HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPAR;
            break;
        case USCI_UART_EVEN_PARITY:
            //Even Parity
            HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;
            HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPAR;
            break;
    }

    //Modulation Control Registers
    HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar;
    HWREG8(baseAddress + OFS_UCAxMCTL) = ((param->firstModReg<<4) +
                                        (param->secondModReg <<1) +
                                        param->overSampling );

    //Asynchronous mode & 8 bit character select & clear mode
    HWREG8(baseAddress + OFS_UCAxCTL0) &=  ~(UCSYNC +
                                             UC7BIT +
                                             UCMODE_3
                                             );

    //Configure  UART mode.
    HWREG8(baseAddress + OFS_UCAxCTL0) |= param->uartMode ;

    //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK
    HWREG8(baseAddress + OFS_UCAxCTL1)  &= ~(UCRXEIE + UCBRKIE + UCDORM +
                                             UCTXADDR + UCTXBRK
                                             );
    return (retVal) ;
}
void USCI_UART_transmitData ( uint16_t baseAddress,
    uint8_t transmitData
    )
{
    //If interrupts are not used, poll for flags
    if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)){
        //Poll for transmit interrupt flag
        while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG));
    }

    HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData;
}

uint8_t USCI_UART_receiveData (uint16_t baseAddress)
{
    //If interrupts are not used, poll for flags
    if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCRXIE)){
        //Poll for receive interrupt flag
        while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCRXIFG));
    }

    return ( HWREG8(baseAddress + OFS_UCAxRXBUF)) ;
}

void USCI_UART_enableInterrupt (uint16_t baseAddress,
    uint8_t mask
    )
{
    uint8_t locMask;

    locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT
        | USCI_UART_TRANSMIT_INTERRUPT));
    HWREG8(baseAddress + OFS_UCAxIE) |= locMask;

    locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
        | USCI_UART_BREAKCHAR_INTERRUPT));
    HWREG8(baseAddress + OFS_UCAxCTL1) |= locMask;
}

void USCI_UART_disableInterrupt (uint16_t baseAddress,
    uint8_t mask
    )
{
    uint8_t locMask;

    if(locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT
        | USCI_UART_TRANSMIT_INTERRUPT))) {
        HWREG8(baseAddress + OFS_UCAxIE) &= ~locMask;
    }

    if(locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
        | USCI_UART_BREAKCHAR_INTERRUPT))) {
        HWREG8(baseAddress + OFS_UCAxCTL1) &= ~locMask;
    }
}

uint8_t USCI_UART_getInterruptStatus (uint16_t baseAddress,
    uint8_t mask)
{
    return ( HWREG8(baseAddress + OFS_UCAxIFG) & mask );
}

void USCI_UART_clearInterruptFlag (uint16_t baseAddress, uint8_t mask)
{
    //Clear the UART interrupt source.
    HWREG8(baseAddress + OFS_UCAxIFG) &= ~(mask);
}

void USCI_UART_enable (uint16_t baseAddress)
{
    //Reset the UCSWRST bit to enable the USCI Module
    HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST);
}

void USCI_UART_disable (uint16_t baseAddress)
{
    //Set the UCSWRST bit to disable the USCI Module
    HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;
}

uint8_t USCI_UART_queryStatusFlags (uint16_t baseAddress,
    uint8_t mask)
{
    return ( HWREG8(baseAddress + OFS_UCAxSTAT) & mask );
}

void USCI_UART_setDormant (uint16_t baseAddress)
{
    HWREG8(baseAddress + OFS_UCAxCTL1) |= UCDORM;
}

void USCI_UART_resetDormant (uint16_t baseAddress)
{
    HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCDORM;
}

void USCI_UART_transmitAddress (uint16_t baseAddress,
    uint8_t transmitAddress)
{
    //Set UCTXADDR bit
    HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXADDR;

    //Place next byte to be sent into the transmit buffer
    HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitAddress;
}

void USCI_UART_transmitBreak (uint16_t baseAddress)
{
    //Set UCTXADDR bit
    HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXBRK;

    //If current mode is automatic baud-rate detection
    if (USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==
        (HWREG8(baseAddress + OFS_UCAxCTL0) &
         USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)){
        HWREG8(baseAddress + OFS_UCAxTXBUF) = USCI_UART_AUTOMATICBAUDRATE_SYNC;
    } else   {
        HWREG8(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;
    }

    //If interrupts are not used, poll for flags
    if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)){
        //Poll for transmit interrupt flag
        while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG));
    }
}

uint32_t USCI_UART_getReceiveBufferAddressForDMA (uint16_t baseAddress)
{
    return ( baseAddress + OFS_UCAxRXBUF );
}

uint32_t USCI_UART_getTransmitBufferAddressForDMA (uint16_t baseAddress)
{
    return ( baseAddress + OFS_UCAxTXBUF );
}


#endif
//*****************************************************************************
//
//! Close the doxygen group for usci_uart_api
//! @}
//
//*****************************************************************************
