Design Rule Verification Report

Date:		9/11/2025
Time:		9:17:57 AM
Elapsed Time:		00:00:41
Filename:		C:\Users\a0488740\AppData\Local\TempReleases\Snapshot\5\MCU178E1.PcbDoc

Warnings:		0
Rule Violations:		0
Waived Violations:		8

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.5mm) (inpolygon),(inpolygon)	0
Clearance Constraint (Gap=0.2mm) (InComponent('USB1')),(OnLayer('Keep-Out Layer'))	0
Clearance Constraint (Gap=0.3mm) (All),(IsKeepOut)	0
Clearance Constraint (Gap=0.2mm) (ISVIA),(ISVIA)	0
Clearance Constraint (Gap=0mm) (InComponentClass('FiducialMark')),(InComponentClass('FiducialMark'))	0
Clearance Constraint (Gap=0.3mm) (InPolygon),(All)	0
Clearance Constraint (Gap=0.15mm) (All),(All)	0
Short-Circuit Constraint (Allowed=Yes) (InComponent('H1') or InComponent('H2')),(InComponent('MH1') or InComponent('MH2'))	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.2032mm) (Max=0.635mm) (Preferred=0.2032mm) (InNetClass('Analog'))	0
Width Constraint (Min=0.127mm) (Max=2.54mm) (Preferred=0.127mm) (All)	0
Routing Layers(All)	0
Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=0.33mm) (PreferredHoleWidth=0.2mm) (MinWidth=0.5mm) (MaxWidth=0.6mm) (PreferedWidth=0.5mm) (IsVia and InAnyComponent)	0
Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=1.016mm) (PreferredHoleWidth=0.25mm) (MinWidth=0.4mm) (MaxWidth=1.651mm) (PreferedWidth=0.45mm) (All)	0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.127mm) (Max=2.54mm) (Prefered=0.15mm) and Width Constraints (Min=0.15mm) (Max=0.381mm) (Prefered=0.27mm) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.254mm) (Conductor Width=0.635mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=0.1mm) (IsVia and InAnyComponent)	0
Minimum Annular Ring (Minimum=0.1mm) (All)	0
Acute Angle Constraint (Minimum=45.000) (All)	0
Hole Size Constraint (Min=0.2mm) (Max=6.3754mm) (All)	0
Pads and Vias to follow the Drill pairs settings	0
Hole To Hole Clearance (Gap=0.25mm) (All),(All)	0
Hole To Hole Clearance (Gap=0mm) (InComponent('H1') or InComponent('H2')),(InComponent('MH1') or InComponent('MH2'))	0
Hole To Hole Clearance (Gap=0mm) (InComponent('USB1')),(InComponent('USB1'))	0
Minimum Solder Mask Sliver (Gap=0.01778mm) (InComponentClass('Logo')),(InComponentClass('Logo'))	0
Minimum Solder Mask Sliver (Gap=0.0762mm) (All),(All)	0
Silk To Solder Mask (Clearance=0mm) (All),(All)	0
Silk To Solder Mask (Clearance=0mm) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All)	0
Silk to Silk (Clearance=0mm) (All),(All)	0
Silk to Silk (Clearance=0mm) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small')))	0
Net Antennae (Tolerance=0mm) (All)	0
Board Clearance Constraint (Gap=0mm) (OnCopper and InComponentClass('Mounting Holes'))	0
Board Clearance Constraint (Gap=0mm) (InComponent('USB1'))	0
Board Clearance Constraint (Gap=0mm) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly)	0
Board Clearance Constraint (Gap=0mm) (OnCopper and IsPoly)	0
Matched Lengths(Tolerance=0.635mm) (InNetClass('FSITX'))	0
Matched Lengths(Tolerance=0.635mm) (InNetClass('FSIRX'))	0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = 0.762mm ) (Disabled)(IsThruComponent),(IsThruComponent)	0
Component Clearance Constraint ( Horizontal Gap = 6.35mm, Vertical Gap = Infinite ) (Disabled)(InComponentClass('Mounting Holes')),(All)	0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0mm ) (Disabled)(HasFootprint('0201') or HasFootprint('0402') or HasFootprint('0508') or HasFootprint('0603') or HasFootprint('0612') or HasFootprint('0805') or HasFootprint('0815') or HasFootprint('0830') or HasFootprint('1206') or HasFootprint('1210') or HasFootprint('1808') or HasFootprint('1812') or HasFootprint('1825') or HasFootprint('2010') or HasFootprint('2220') or HasFootprint('2225') or HasFootprint('2512') or HasFootprint('2728') or HasFootprint('3518')),(HasFootprint('0201') or HasFootprint('0402') or HasFootprint('0508') or HasFootprint('0603') or HasFootprint('0612') or HasFootprint('0805') or HasFootprint('0815') or HasFootprint('0830') or HasFootprint('1206') or HasFootprint('1210') or HasFootprint('1808') or HasFootprint('1812') or HasFootprint('1825') or HasFootprint('2010') or HasFootprint('2220') or HasFootprint('2225') or HasFootprint('2512') or HasFootprint('2728') or HasFootprint('3518'))	0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (OnBottomSilkscreen),(OnTopSilkscreen)	0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponentClass('Logo')),(InComponentClass('Logo'))	0
Component Clearance Constraint ( Horizontal Gap = 0.1mm, Vertical Gap = 0.1mm ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C')))	0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (Disabled)(IsThruComponent),(IsSMTComponent)	0
Component Clearance Constraint ( Horizontal Gap = 1.27mm, Vertical Gap = 0.254mm ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark'))	0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponentClass('Header')),(InComponentClass('Shunt'))	0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponentClass('Logo')),(All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	0

Waived Violations	Count
Minimum Annular Ring (Minimum=0.1mm) (All)	6
Board Clearance Constraint (Gap=0mm) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly)	2
Total	8

Rule Violations

Waived Violations

Minimum Annular Ring (Minimum=0.1mm) (All)
Minimum Annular Ring: (No Ring) Pad USB1-1(16.19501mm,-6.27995mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:54:39 AM USB footprint cannot be changed, no issues identified.
Minimum Annular Ring: (No Ring) Pad USB1-1(16.52001mm,-6.87996mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:55:10 AM USB footprint cannot be changed, no issues identified.
Minimum Annular Ring: (No Ring) Pad USB1-2(7.88001mm,-6.87996mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:55:17 AM USB footprint cannot be changed, no issues identified.
Minimum Annular Ring: (No Ring) Pad USB1-2(8.20501mm,-6.27995mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:55:21 AM USB footprint cannot be changed, no issues identified.
Minimum Annular Ring: (No Ring) Pad USB1-3(18.05001mm,-1.57995mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:55:26 AM USB footprint cannot be changed, no issues identified.
Minimum Annular Ring: (No Ring) Pad USB1-4(6.35001mm,-1.57995mm) on Multi-Layer (Annular Ring missing on Top Layer) Waived by Brennan Hartigan at 9/11/2025 8:55:30 AM USB footprint cannot be changed, no issues identified.

Board Clearance Constraint (Gap=0mm) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly)
Board Outline Clearance(Outline Edge): (Collision < 0.254mm) Between Board Edge And Text ".Layer_Name" (-10.6128mm,-130.63594mm) on Bottom Signal Waived by Brennan Hartigan at 9/11/2025 8:53:59 AM Overlapping text in file details
Board Outline Clearance(Outline Edge): (Collision < 0.254mm) Between Board Edge And Text ".Layer_Name" (-10.6128mm,-130.63594mm) on Top Signal Waived by Brennan Hartigan at 9/11/2025 8:54:32 AM Overlapping text in file details