/**********************************************************************
* File: F28055_nonBIOS_ram.cmd -- Linker command file for non-DSP/BIOS
* code with DSP in jump-to-M0SARAM boot mode.
*
* History:
*   07/09/12 - original (D. Alter)
**********************************************************************/

MEMORY
{
PAGE 0:    /* Program Memory */
   BEGIN_M0             : origin = 0x000000, length = 0x000002    /* Part of M0SARAM.  Used for "Boot to M0" bootloader mode. */
   L0DPSARAM            : origin = 0x008000, length = 0x000800    /* L0 DPSARAM, Z1 or Z2 secure, CLA Data RAM 2 */
   L3DPSARAM            : origin = 0x009000, length = 0x001000    /* L3 DPSARAM, Z1 or Z2 secure, CLA Prog RAM */
   CLA_ROM          (R) : origin = 0x00F000, length = 0x001000    /* CLA Data ROM */
   DCSM_OTP_Z2_P0   (R) : origin = 0x3D7800, length = 0x000006    /* Part of Z2 OTP.  LinkPointer, JTAG lock, Boot Mode */
   DCSM_ZSEL_Z2_P0  (R) : origin = 0x3D7810, length = 0x000010    /* Part of Z2 OTP.  Z2 password locations, Flash and RAM partitioning */
   DCSM_OTP_Z1_P0   (R) : origin = 0x3D7A00, length = 0x000006    /* Part of Z1 OTP.  LinkPointer, JTAG lock, backup Boot Mode */
   DCSM_ZSEL_Z1_P0  (R) : origin = 0x3D7A10, length = 0x000010    /* Part of Z1 OTP.  Z1 password locations, Flash and RAM partitioning */
   FLASH_ABCDEFGHIJ (R) : origin = 0x3E8000, length = 0x00FFFE    /* FLASH, All sectors combined */
   BEGIN_FLASH      (R) : origin = 0x3F7FFE, length = 0x000002    /* Part of FLASH Sector A.  Used for "Jump to flash" bootloader mode. */
   IQTABLES         (R) : origin = 0x3FDB52, length = 0x000b50    /* Part of Boot ROM */
   IQTABLES2        (R) : origin = 0x3FE6A2, length = 0x00008C    /* Part of Boot ROM */
   IQTABLES3        (R) : origin = 0x3FE72E, length = 0x0000AA    /* Part of Boot ROM */
   RESET            (R) : origin = 0x3FFFC0, length = 0x000002    /* Part of Boot ROM */

 PAGE 1 :   /* Data Memory */
   M0SARAM              : origin = 0x000002, length = 0x0003FE    /* M0 SARAM */
   M1SARAM              : origin = 0x000400, length = 0x000400    /* M1 SARAM */
   CLA1_TO_CPU_MSGRAM   : origin = 0x001480, length = 0x000080    /* CLA1 to CPU message RAM */
   CPU_TO_CLA1_MSGRAM   : origin = 0x001500, length = 0x000080    /* CPU to CLA1 message RAM */
   L1DPSARAM            : origin = 0x008800, length = 0x000400    /* L1 DPSARAM, Z1 or Z2 secure, CLA Data RAM 0 */
   L2DPSARAM            : origin = 0x008C00, length = 0x000400    /* L2 DPSARAM, Z1 or Z2 secure, CLA Data RAM 1 */
}

 
SECTIONS
{
/*** Compiler Required Sections ***/

  /* Program memory (PAGE 0) sections */
   .text              : > L0DPSARAM,             PAGE = 0
   .cinit             : > L0DPSARAM,             PAGE = 0
   .const             : > L0DPSARAM,             PAGE = 0
   .econst            : > L0DPSARAM,             PAGE = 0
   .pinit             : > L0DPSARAM,             PAGE = 0
   .reset             : > RESET,                 PAGE = 0, TYPE = DSECT  /* We are not using the .reset section */
   .switch            : > L0DPSARAM,             PAGE = 0

  /* Data Memory (PAGE 1) sections */
   .bss               : > M0SARAM,               PAGE = 1
   .ebss              : > M0SARAM,               PAGE = 1
   .cio               : > M0SARAM,               PAGE = 1
   .stack             : > M1SARAM,               PAGE = 1
   .sysmem            : > M1SARAM,               PAGE = 1
   .esysmem           : > M1SARAM,               PAGE = 1

/*** User Defined Sections ***/
   codestart          : > BEGIN_M0,              PAGE = 0                /* Used by file CodeStartBranch.asm */
}

/******************* end of file ************************/
