;***************************************************************@@ms*//*! \file
;                                c6727dsk.inc
;\brief   Generic Bootloader example code for the C6727 EVM-board
;
;@@md
;         Definitions for the bootloader-assembler file.
;
;*//*====================================================================@@mi==
;  PROJECTDESCRIPTION:     $ProjectName: Generic C6727$
;  PROCESSOR:              C6727
;  PROJECTVERSION:         $ProjectRevision: V1.0     $
;  KOMPONENT:              Bootloader
;  NAME OF PROGRAMMER:     $Author: Dieter Weuffen $
;  COMPILER:               -
;  VERSIONSNUMMER:         $Revision: V1.0         $
;------------------------------------------------------------------------@@mu--
;  FILENAME:               $Workfile c6727dsk.inc $
;  VERSIONNUMBER:          $Revision$
;  LAST CHANGE:            $Date$
;    ---*/ /*---
;  HISTORY:                $Log$
;
;************************************************************************@@me**


; some system and boot loader constants
COPY_TABLE                     .equ                    90000400h ; start address of the hex6x generated section table in the flash
CFGPIN0                        .equ                    40000000h ; register address for sampled state of config pins 0..7 at hw-reset time
CFGPIN1                        .equ                    40000004h ; register address for sampled state of config pins 8..15 at hw-reset time
CFGPIN1_nHCS                   .equ                    00000020h ; /HCS bit

CFGHPI                         .equ                    40000008h ; HPI config register
CFGHPI_ENA                     .equ                    00000001h ; enable bit for the CFGHPI register

; values for the memory location _parallel_flash_signature
TRANSFER_MAGIC_8               .equ                    00000000h
TRANSFER_MAGIC_16              .equ                    01010101h
TRANSFER_REQUEST               .equ                    02020202h
TRANSFER_DONE                  .equ                    03030303h

; Start address of peripherals
INTERNAL_ROM_PAGE_0            .equ                     0X00000000  ; Start: Internal ROM Page 0 (256K Bytes) End: 0x0003FFFF Byte and Word
INTERNAL_ROM_PAGE_1            .equ                     0x00040000  ; Start: Internal ROM Page 1 (128K Bytes) End: 0x0005FFFF Byte and Word
INTERNAL_RAM_PAGE_0            .equ                     0x10000000  ; Start: Internal RAM Page 0 (256K Bytes) End: 0x1003FFFF Byte and Word
MEMORY_N_CACHE_CONTROL_REG_START   .equ                 0x20000000  ; Start: Memory and Cache Control Registers End: 0x2000001F Word Only
EMULATION_CONTROL_REG_START    .equ                     0x30000000  ; Start: Emulation Control Registers (Do Not Access) End: 0x3FFFFFFF Word Only
DEVICE_CONFIG_REG_START        .equ                     0x40000000  ; Start: Device Configuration Registers End: 0x40000083 Word Only
PLL_REG_START                  .equ                     0x41000000  ; Start: PLL Control Registers End: 0x4100015F Word Only
RTI_REG_START                  .equ                     0x42000000  ; Start: Real-time Interrupt (RTI) Control Registers End: 0x420000A3 Word Only
UHPI_REG_START                 .equ                     0x43000000  ; Start: Universal Host-Port Interface (UHPI) Registers End: 0x43000043 Word Only
McASP0_REG_START               .equ                     0x44000000  ; Start: McASP0 Control Registers End: 0x440002BF Word Only
McASP1_REG_START               .equ                     0x45000000  ; Start: McASP1 Control Registers End: 0x450002BF Word Only
McASP2_REG_START               .equ                     0x46000000  ; Start: McASP2 Control Registers End: 0x460002BF Word Only
SPI0_REG_START                 .equ                     0x47000000  ; Start: SPI0 Control Registers End: 0x4700007F Word Only
SPI1_REG_START                 .equ                     0x48000000  ; Start: SPI1 Control Registers End: 0x4800007F Word Only
I2C0_REG_START                 .equ                     0x49000000  ; Start: I2C0 Control Registers End: 0x4900007F Word Only
I2C1_REG_START                 .equ                     0x4A000000  ; Start: I2C1 Control Registers End: 0x4A00007F Word Only
McASP0_DMA_REG_START           .equ                     0x54000000  ; Start: McASP0 DMA Port (any address in this range) End: 0x54FFFFFF Word Only
McASP1_DMA_REG_START           .equ                     0x55000000  ; Start: McASP1 DMA Port (any address in this range) End: 0x55FFFFFF Word Only
McASP2_DMA_REG_START           .equ                     0x56000000  ; Start: McASP2 DMA Port (any address in this range) End: 0x56FFFFFF Word Only
dMAX_REG_START                 .equ                     0x60000000  ; Start: dMAX Control Registers End: 0x6000008F Word Only
MAX0_EVENT_ENTRY               .equ                     0x61008000  ; Start: MAX0 (HiMAX) Event Entry Table End: 0x6100807F Byte and Word
MAX0_TRANSFER_ENTRY            .equ                     0x610080A0  ; Start: MAX0 (HiMAX) Transfer Entry Table End: 0x610081FF Byte and Word
MAX1_EVENT_ENTRY               .equ                     0x62008000  ; Start: MAX1 (LoMAX) Event Entry Table End: 0x6200807F Byte and Word
MAX1_TRANSFER_ENTRY            .equ                     0x620080A0  ; Start: MAX1 (LoMAX) Transfer Entry Table End: 0x620081FF Byte and Word
SDRAM_SPACE_START              .equ                     0x80000000  ; Start: External SDRAM space on EMIF End: 0x8FFFFFFF Byte and Word
FLASH_SPACE_START              .equ                     0x90000000  ; Start: External Asynchronous / Flash space on EMIF End: 0x9FFFFFFF Byte and Word
EMIF_REG_START                 .equ                     0xF0000000  ; Start: EMIF Control Registers End: 0xF00000BF Word Only(
                                        
                                        
EMIF_AWCCR                     .equ                    (EMIF_REG_START+0x04)           ; async wait cycle config
EMIF_SDCR                      .equ                    (EMIF_REG_START+0x08)           ; SDRAM config reg
EMIF_SDRCR                     .equ                    (EMIF_REG_START+0x0c)           ; SDRAM refresh control
EMIF_A1CR                      .equ                    (EMIF_REG_START+0x10)           ; asynchronous 1 config
EMIF_SDTIMR                    .equ                    (EMIF_REG_START+0x20)           ; SDRAM timing register
EMIF_SDSRETR                   .equ                    (EMIF_REG_START+0x3c)           ; SDRAM self refresh exit timing register
EMIF_EIRR                      .equ                    (EMIF_REG_START+0x40)           ; interrupt raw
EMIF_EIMR                      .equ                    (EMIF_REG_START+0x44)           ; interrupt mask reg
EMIF_EIMSR                     .equ                    (EMIF_REG_START+0x48)           ; interrupt mask set
EMIF_EIMCR                     .equ                    (EMIF_REG_START+0x4c)           ; interrupt mask clear reg

MCASP0_PFUNC                   .equ                    (McASP0_REG_START+0x10)
MCASP0_PDIR                    .equ                    (McASP0_REG_START+0x14)
MCASP0_PDOUT                   .equ                    (McASP0_REG_START+0x18)
MCASP0_PDIN                    .equ                    (McASP0_REG_START+0x1c)
MCASP0_PDSET                   .equ                    (McASP0_REG_START+0x1c)
MCASP0_PDCLR                   .equ                    (McASP0_REG_START+0x20)
MCASP1_PFUNC                   .equ                    (McASP1_REG_START+0x10)
MCASP1_PDIR                    .equ                    (McASP1_REG_START+0x14)
MCASP1_PDOUT                   .equ                    (McASP1_REG_START+0x18)
MCASP1_PDIN                    .equ                    (McASP1_REG_START+0x1c)
MCASP1_PDSET                   .equ                    (McASP1_REG_START+0x1c)
MCASP1_PDCLR                   .equ                    (McASP1_REG_START+0x20)
MCASP2_PFUNC                   .equ                    (McASP2_REG_START+0x10)
MCASP2_PDIR                    .equ                    (McASP2_REG_START+0x14)
MCASP2_PDOUT                   .equ                    (McASP2_REG_START+0x18)
MCASP2_PDIN                    .equ                    (McASP2_REG_START+0x1c)
MCASP2_PDSET                   .equ                    (McASP2_REG_START+0x1c)
MCASP2_PDCLR                   .equ                    (McASP2_REG_START+0x20)


PLL_BASE_ADDR                  .equ                    PLL_REG_START
PLL_PID                        .equ                    ( PLL_BASE_ADDR+0x000 )         ; identification
PLL_CSR                        .equ                    ( PLL_BASE_ADDR+0x100 )         ; control/status
PLL_M                          .equ                    ( PLL_BASE_ADDR+0x110 )         ; multiplier 1...25
PLL_DIV0                       .equ                    ( PLL_BASE_ADDR+0x114 )         ;
PLL_DIV1                       .equ                    ( PLL_BASE_ADDR+0x118 )         ;
PLL_DIV2                       .equ                    ( PLL_BASE_ADDR+0x11C )         ;
PLL_DIV3                       .equ                    ( PLL_BASE_ADDR+0x120 )         ;
PLL_CMD                        .equ                    ( PLL_BASE_ADDR+0x138 )         ; controller command
PLL_STAT                       .equ                    ( PLL_BASE_ADDR+0x13c )         ; controller status
ALN_CTL                        .equ                    ( PLL_BASE_ADDR+0x140 )         ; controller clock align control
CKEN                           .equ                    ( PLL_BASE_ADDR+0x148 )         ; clock enable control
CKSTAT                         .equ                    ( PLL_BASE_ADDR+0x14c )         ; clock status
SYSTAT                         .equ                    ( PLL_BASE_ADDR+0x150 )         ; SYSCLK status

CSR_PLLEN                      .equ                    0x00000001
CSR_PLLPWRDN                   .equ                    0x00000010
CSR_OSCPWRDN                   .equ                    0x00000004
CSR_PLLRST                     .equ                    0x00000008
CSR_PLLPWRDN                   .equ                    0x00000010
CSR_PLLSTABLE                  .equ                    0x00000040
DIV_ENABLE                     .equ                    0x00008000
CMD_GOSET                      .equ                    0x00000001

; UHPI
UHPI                           .equ                    (UHPI_REG_START+0x08)   ; Configuration Register
CFGHPIAMSB                     .equ                    (UHPI_REG_START+0x0C)   ; Most Significant Byte of UHPI Address
CFGHPIAUMB                     .equ                    (UHPI_REG_START+0x10)   ; Upper Middle Byte of UHPI Address
;UHPI Internal Registers       
PID                            .equ                    (UHPI_REG_START+0x00)   ; Peripheral ID Register
PWREMU                         .equ                    (UHPI_REG_START+0x04)   ; Power and Emulation Management Register
GPIOINT                        .equ                    (UHPI_REG_START+0x08)   ; General Purpose I/O Interrupt Control Register
GPIOEN                         .equ                    (UHPI_REG_START+0x0C)   ; General Purpose I/O Enable Register
GPIODIR1                       .equ                    (UHPI_REG_START+0x10)   ; General Purpose I/O Direction Register 1
GPIODAT1                       .equ                    (UHPI_REG_START+0x14)   ; General Purpose I/O Data Register 1
GPIODIR2                       .equ                    (UHPI_REG_START+0x18)   ; General Purpose I/O Direction Register 2
GPIODAT2                       .equ                    (UHPI_REG_START+0x1C)   ; General Purpose I/O Data Register 2
GPIODIR3                       .equ                    (UHPI_REG_START+0x20)   ; General Purpose I/O Direction Register 3
GPIODAT3                       .equ                    (UHPI_REG_START+0x24)   ; General Purpose I/O Data Register 3
HPIC                           .equ                    (UHPI_REG_START+0x30)   ; Control Register
HPIAW                          .equ                    (UHPI_REG_START+0x34)   ; Write Address Register
HPIAR                          .equ                    (UHPI_REG_START+0x38)   ; Read Address Register

; ### EOF ###
