Waived DRC Error Report
C:/srf04/Agama/Agama_EM_Designs/CC26x2RBEM-7ID/Cadence/Allegro/CC26x2RBEM-7ID.brd
Thu Dec 12 07:57:19 2019

DRC Error Count Summary
DRC Error Type,DRC Error Count
Package to Package,1
Etch to Pad,1
Etch to Etch,1
Etch to Pad (Same Net),2
Total DRC Errors,5

Detailed DRC Errors
Constraint Name,DRC Marker Location,Required Value,Actual Value,Constraint Source,Constraint Source Type,Element 1,Element 2,Comment
Package to Package Spacing,(123.575 125.725),0 MM,0.6 MM,NONE,DESIGN,Shape "C14  Package Geometry/Place_Bound_Top",Shape "C24  Package Geometry/Place_Bound_Top",SMA/Antenna selector
Shape to SMD Pin Spacing,(123.555 132.525),0.15 MM,0 MM,DEFAULT,NET SPACING CONSTRAINTS,Shape "Gnd  Etch/Top",Pin "A1.1 (N316022)",PCB antenna
Line to Shape Spacing,(123.325 132.275),0.15 MM,0 MM,DEFAULT,NET SPACING CONSTRAINTS,Shape "Gnd  Etch/Top",Vertical Line Segment "N316022  Etch/Top",PCB antenna
Shape to SMD Pin Same Net Spacing,(127.205 132.525),0.15 MM,0 MM,DEFAULT,SAME NET CONSTRAINTS,Shape "Gnd  Etch/Top",Pin "A1.3 (Gnd)",PCB antenna
Shape to SMD Pin Same Net Spacing,(125.005 132.525),0.15 MM,0 MM,DEFAULT,SAME NET CONSTRAINTS,Shape "Gnd  Etch/Top",Pin "A1.2 (Gnd)",PCB antenna

