v2 -  11/13/2019: Optimized DDR traces per 370HR stack-up & ran xls checks vs LPDDR4 Design Guide App Note
v3 -  11/19/2019: Update MCU_0V85/MCU_RAM_0V85 on layer 1/4/5 to improve Z
v4 -  12/3/2019 : Qty 2 each 3T-1uF caps moved under soc for core and cpu power rails
v5 -  12/3/2019 : Change top side gnd
v6 -  12/5/2019 : V4 with L2/L4 DQ bytes at ~40ohms.  Did not start with V5 since it had some side effects on floods
v7 -  12/17/2019 : V5 with additional power and gnd vias on CPU rail to reduce inductance
v8 -  12/18/2019 : V6 with DQS/CK = ~80Ohm, CA SE signals = ~40Ohm. This should get all LPDDR signals near the 40-ohm or 80-ohm targets.
                  The limiting factor is layers 4/7 at max trace width of 6.4 mils and then layer 2 and 9 traces width set to yield
                  approx same Z as layer 4/7.  Allegro reports the Z at ~41ohms.
v9 -  02/05/2020 : Remove two vias in MCU_0V85 that were shorting to GND at U1027
v9 -  02/27/2020 : Truncated brd filename from "j7es_ref_dsn_TTM_10L_370HR_100819_16p6" to 
                  "j7es_ref_dsn_TTM_10L_370HR" by removing non-essential info,
 		  		  stackup rev date "100819" and Allegro tool ver "16p6"
                  This did NOT change the PWB Rev on box.
v10 - 03/11/2020 : Add GND stitch vias for diff pair signals and transition vias.
                   Add plane cutouts under AC caps, filters and DP connector.
v11  - 06/15/2020 : Add TIDEP-01020 to title.