# Design Rule Verification Report

Date: |  | 3/15/2023
Time: |  | 3:41:21 AM
Elapsed Time: |  | 00:00:01
Filename: |  | C:\TI_Projects\Sitara_Projects\Boosterpack\BP-AM2BLDCSERVO\Altium_Project\BP-AM2BLDCSERVO_E2\layout\PROC152E2.PcbDoc
Warnings: |  | 0
Rule Violations: |  | 2

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) | 2
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) | 0
Total | 2

Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (3.85mil < 3.937mil) Between Pad C4-1(3119.594mil,1378.741mil) on Bottom Layer And Via (3062.594mil,1415.001mil) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [3.85mil]
Minimum Solder Mask Sliver Constraint: (3.85mil < 3.937mil) Between Pad C4-1(3119.594mil,1378.741mil) on Bottom Layer And Via (3062.594mil,1455.001mil) from Top Layer to Bottom Layer [Bottom Solder] Mask Sliver [3.85mil]

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