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# Design Rule Verification Report

Date | : | 9/22/2014
Time | : | 7:11:26 PM
Elapsed Time | : | 00:00:02
Filename | : | D:\TIDA-00289\Completed_E3\Design Files_TIDA-00289\TIDA-00289.PcbDoc
Warnings | : | 0
Rule Violations | : | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=12mil) (InPolygon),(IsTrack and IsThruPin and IsSMTPin and IsThruPin) | 0
Clearance Constraint (Gap=8mil) (IsVia),(IsSMTPin) | 0
Clearance Constraint (Gap=8mil) (IsVia),(IsVia) | 0
Net Antennae (Tolerance=0mil) (All) | 0
Hole To Hole Clearance (Gap=10mil) (All),(All) | 0
Hole Size Constraint (Min=8mil) (Max=251mil) (All) | 0
Minimum Annular Ring (Minimum=5.905mil) (All) | 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) | 0
Un-Routed Net Constraint ( (All) ) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=12mil) (MinWidth=26mil) (MaxWidth=40mil) (PreferedWidth=26mil) (All) | 0
Routing Layers(All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=8mil) (All) | 0
Clearance Constraint (Gap=8mil) (All),(All) | 0
Clearance Constraint (Gap=15mil) (InPolygon),(InPolygon) | 0
Clearance Constraint (Gap=7mil) ((InPadClass('Less than 9 Mil Clearance'))),((InPadClass('All Pads'))) | 0
Total | 0