Protel Design System Design Rule Check
PCB File : D:\TIDA-00289\Completed_E3\Design Files_TIDA-00289\TIDA-00289.PcbDoc
Date     : 9/22/2014
Time     : 7:11:26 PM

Processing Rule : Clearance Constraint (Gap=12mil) (InPolygon),(IsTrack and IsThruPin and IsSMTPin and IsThruPin)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (IsVia),(IsSMTPin)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (IsVia),(IsVia)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=8mil) (Max=251mil) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=5.905mil) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=12mil) (MinWidth=26mil) (MaxWidth=40mil) (PreferedWidth=26mil) (All)
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=100mil) (Preferred=8mil) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=15mil) (InPolygon),(InPolygon)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7mil) ((InPadClass('Less than 9 Mil Clearance'))),((InPadClass('All Pads')))
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:02