(NETLIST)
(FOR DRAWING: M:/pcb/cadence/WV5_rD/WV5_rD.brd)
(GENERATED BY: ALLEGRO 16.2 p005 (v16-2-57E))
(Thu Mar 10 12:00:09 2011)
$PACKAGES
0402_TRIPAD ! RESISTOR_TRIPAD_0402_TRIPAD_0 ! 0 ; R249 R250 R251 R252 R253 ,
        R254 R255 R256 
0603_TRIPAD ! RESISTOR_TRIPAD_0603_TRIPAD_0 ! 0 ; R43 R53 R276 
0603_TRIPAD ! RESISTOR_TRIPAD_0603_TRIPAD_10K ! 10K ; R44 
0603_TRIPAD ! RESISTOR_TRIPAD_0603_TRIPAD_1K ! 1K ; R292 
0805 ! 'C-POLARISED_0805_10UF' ! 10uF ; C122 C196 
128TQFP ! 'CYPRESS CY7C64613-80NC_128TQFP_' ! 'Cypress CY7C68013A-128AXC' ; ,
        U19 
BGA_165_13X15_1P0 ! IDT71P71804_BGA_165_13X15_1P0_I ! IDT71P71804 ; U3 U4 ,
        U5 U6 
BGA_668_27X27_1P0 ! 'XC4VLX25-11FFG668 _1_BGA_668_27' ! 'XC4VLX25-11FFG668' ,
        ; U1 
C0402 ! 'C-NON-POL_C0402_100N' ! 100n ; C74 C75 C76 C77 C78 C79 C80 C81 C82 ,
        C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 ,
        C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 ,
        C113 C114 C115 C116 C117 C118 C119 C123 C124 C125 C126 C127 C128 ,
        C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 ,
        C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 ,
        C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167 ,
        C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 ,
        C186 C187 C188 C189 C190 C191 C192 C193 C211 C217 
C0402 ! 'CAPACITOR NON-POL_C0402_0.01UF' ! '0.01uF' ; C59 C120 C194 C208 ,
        C209 C210 C212 C213 C214 C215 C216 C220 C221 
C0402 ! 'CAPACITOR NON-POL_C0402_100N' ! 100n ; C49 C50 C51 C52 C53 C54 C55 ,
        C56 C57 C60 C65 C197 C198 C204 C205 C206 C207 
C0603 ! 'C-NON-POL_C0603_100N' ! 100n ; C2 C5 C22 C23 C31 C33 C44 C45 C48 ,
        C61 C63 C64 C66 C201 C240 
C0603 ! 'C-NON-POL_C0603_10N' ! 10n ; C3 C8 C11 C24 C25 C26 C35 C38 C202 
C0603 ! 'C-NON-POL_C0603_2.2N' ! '2.2n' ; C62 
C0603 ! 'CAPACITOR NON-POL_C0603_0.001UF' ! '0.001uF' ; C199 
C1206 ! 'C-NON-POL_C1206_3.3UF' ! '3.3uF' ; C6 C7 C9 C10 C36 C37 
C1206 ! 'CAPACITOR NON-POL_C1206_12PF' ! 12pF ; C68 C69 
C1206 ! 'CAPACITOR NON-POL_C1206_4.7N' ! '4.7n' ; C67 
C3216 ! 'C-POLARISED_C3216_2.2UF' ! '2.2uF' ; C58 
C6032 ! 'C-POLARISED_C6032_10UF' ! 10uF ; C1 C19 C20 C21 C30 C32 C34 C43 ,
        C47 C200 
C6032 ! 'C-POLARISED_C6032_220UF' ! 220uF ; C121 C195 
C6032 ! 'C-POLARISED_C6032_22UF' ! 22uF ; C12 C27 C28 C29 C39 C203 
C6032 ! 'C-POLARISED_C6032_47UF' ! 47uF ; C4 C46 
C7343H ! 'C-POLARISED_C7343H_47UF' ! 47uF ; C13 C14 C15 C16 C17 C18 C40 C41 ,
        C42 
'CHOKE_CM2545-B' ! 'INDUCTOR CM CHOKE_CHOKE_CM2545-' ! 'CM CHOKE' ; L1 
DO_SMA ! 'DIODE ZENER_DO_SMA_SMAZ6V2' ! SMAZ6V2 ; D18 
DR127_8R2 ! 'INDUCTOR PWR_DR127_8R2_22UH' ! 22uH ; L10 
DR127_8R2 ! 'INDUCTOR PWR_DR127_8R2_8.86UH' ! '8.86uH' ; L3 L4 
E5387A_PROBE ! 'E3587A HEADER_E5387A_PROBE_E358' ,
        ! 'E3587A SOFT TOUCH HEADER' ; J10 
HC49US ! CRYSTAL_HC49US_24MHZ ! 24MHz ; Y2 
IND_SMD_7032 ! 'INDUCTOR PWR_IND_SMD_7032_10UH' ! 10uH ; L2 L5 L6 L7 L9 L18 
JACK_POWER ! 'CONN PWR JACK_JACK_POWER_CONN P' ! 'CONN PWR JACK' ; J2 
LED_T3_RA ! LED_SNGLE_PANEL_LED_T3_RA_GREEN ! GREEN ; LD1 
MICRO_BGA_2X2 ! SI8409DB_MICRO_BGA_2X2_SI8409DB ! Si8409DB ; Q2 
MICTOR_38_VF ! 'CONN 38 PIN MICTOR_0_MICTOR_38_' ! 'CONN 38 PIN MICTOR' ; ,
        J5 
MSOP8 ! LM95235_MSOP8_LM95235 ! LM95235 ; U20 
OSC_100M_5X7 ! 'OSC-SM_OSC_100M_5X7_OSC (SM)' ! 'OSC (SM)' ; Y1 
R0402 ! RESISTOR_R0402_0 ! 0 ; R274 R275 
R0402 ! RESISTOR_R0402_10K ! 10K ; R88 R89 R151 R152 R155 R156 R159 R163 ,
        R184 R185 R186 R187 R217 R219 R227 R229 R238 R247 
R0402 ! RESISTOR_R0402_22 ! 22 ; R277 
R0402 ! RESISTOR_R0402_249 ! 249 ; R65 R70 R105 R124 
R0402 ! RESISTOR_R0402_51 ! 51 ; R66 R67 R68 R69 R71 R72 R73 R74 R75 R76 ,
        R78 R81 R82 R85 R86 R87 R91 R92 R94 R97 R98 R101 R103 R104 R106 ,
        R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 ,
        R120 R121 R122 R123 R125 R126 R127 R128 R129 R130 R131 R132 R133 ,
        R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 ,
        R147 R148 R149 R150 R153 R154 R157 R158 R160 R161 R162 R164 R165 ,
        R166 R167 R169 R170 R171 R210 R211 R212 R213 R214 R215 R216 R218 ,
        R220 R221 R222 R223 R224 R225 R226 R228 R230 R231 R232 R233 R234 ,
        R235 R236 R237 R239 R240 R241 R242 R243 R244 R245 R246 
R0603 ! RESISTOR_R0603_0 ! 0 ; R42 R248 R273 R294 R295 
R0603 ! RESISTOR_R0603_10 ! 10 ; R2 
R0603 ! 'RESISTOR_R0603_10.2K' ! '10.2K' ; R7 R13 R15 R17 
R0603 ! RESISTOR_R0603_100 ! 100 ; R189 R190 R191 R192 R278 
R0603 ! RESISTOR_R0603_100K ! 100K ; R11 
R0603 ! RESISTOR_R0603_10K ! 10k ; R19 R20 R32 R33 R34 R35 R36 R54 R172 ,
        R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R263 R264 ,
        R265 R266 R267 R268 R269 R270 R279 R280 R288 R293 R296 R297 R298 
R0603 ! 'RESISTOR_R0603_15.4K' ! '15.4K' ; R23 R286 
R0603 ! 'RESISTOR_R0603_18.2K' ! '18.2K' ; R291 
R0603 ! RESISTOR_R0603_1K ! 1K ; R5 R6 R12 R25 R283 
R0603 ! 'RESISTOR_R0603_22.1K' ! '22.1K' ; R8 R16 R55 
R0603 ! 'RESISTOR_R0603_30.1K' ! '30.1K' ; R24 R285 
R0603 ! 'RESISTOR_R0603_32.4K' ! '32.4K' ; R14 R22 R284 
R0603 ! RESISTOR_R0603_330 ! 330 ; R26 R27 R28 R29 R30 R31 R40 R193 R194 ,
        R195 R196 R197 R198 R257 R258 R259 R260 R261 R262 R271 R272 
R0603 ! RESISTOR_R0603_330R ! 330R ; R281 R287 
R0603 ! 'RESISTOR_R0603_4.12K' ! '4.12K' ; R1 R9 R10 R21 R282 
R0603 ! 'RESISTOR_R0603_4.7K' ! '4.7K' ; R41 R45 R290 
R0603 ! RESISTOR_R0603_47 ! 47 ; R38 R39 R46 R47 R48 R289 
R0603 ! RESISTOR_R0603_487 ! 487 ; R3 
R0603 ! RESISTOR_R0603_51 ! 51 ; R37 R49 R57 R58 R59 R60 R63 R64 R77 R83 ,
        R84 R90 R199 R200 R201 R202 
R0603 ! RESISTOR_R0603_680 ! 680 ; R4 
R0603 ! 'RESISTOR_R0603_9.09K' ! '9.09K' ; R18 
R1206 ! CHOKE_R1206_CHOKE ! CHOKE ; L8 L11 L12 L13 L14 L16 L17 
R1206 ! LED_SNGLE_PANEL_R1206_GREEN ! GREEN ; LD2 LD3 LD4 LD5 LD7 LD11 LD12 ,
        LD13 LD14 LD15 LD16 LD17 LD18 
R1206 ! LED_SNGLE_PANEL_R1206_RED ! RED ; LD6 LD19 LD20 
R1206 ! RESISTOR_R1206_100K ! 100K ; R50 
R1206 ! RESISTOR_R1206_1M ! 1M ; R56 
R1206 ! 'RESISTOR_R1206_2.2K' ! '2.2K' ; R51 R52 
RES472 ! RESISTOR_RES472_1 ! 1 ; R168 
SHDR6X1 ! 'CONN 6 PIN SINGLE ROW_SHDR6X1_C' ! 'CONN 6 PIN SINGLE ROW' ; J3 
SMB ! 'DIODE SM SCHOTTKY_SMB_B130LB-13' ! 'B130LB-13-F' ; D3 D11 D12 D13 ,
        D16 D21 
SMB ! 'DIODE SM SCHOTTKY_SMB_B340LB-13' ! 'B340LB-13-F' ; D4 D5 D17 
SM_7PIN_FTR ! 2MM_7PIN_HEADER_SM_7PIN_FTR_2MM ! 2MM_7PIN_HEADER ; U27 U28 
SM_JUMPER ! JUMPER_SM_SM_JUMPER_JUMPER_SM ! jumper_sm ; JP5 JP6 JP7 JP8 JP9 ,
        JP10 JP11 JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19 JP20 JP21 JP22 ,
        JP23 JP24 JP25 JP26 JP27 JP28 JP29 JP30 JP31 JP32 JP33 JP34 JP35 ,
        JP36 JP37 JP38 
SO8 ! LP2996_SO8_LP2996 ! LP2996 ; U25 U26 
SOD123 ! 'DIODE TH 1N4148_SOD123_1N4148W' ! 1N4148W ; D2 D9 D10 D15 D20 
SOD123 ! 'DIODE TH 1N4148_SOD123_BAT42W' ! BAT42W ; D8 
SOIC8 ! 24C02/SO8_0_SOIC8_24C02 ! 24C02 ; U22 
'SOT-23' ! 'TRANSISTOR NPN BC817 SMD_SOT-23' ! 'BC817-25-7-F' ; Q1 Q3 
SOT223 ! 'LM1117MPX_SOT223_LM1117MPX-3.3' ! 'LM1117MPX-3.3' ; U14 U16 
'SOT23-STX' ! '74LVC1G07_SOT23-STX_74LVC1G07' ! 74LVC1G07 ; U29 U31 
'SOT23-STX' ! '74LVC1G17_SOT23-STX_74LVC1G07' ! 74LVC1G07 ; U17 
'SOT23-STX' ! 'LM3722_SOT23-STX_LM3722' ! LM3722 ; U21 
SOT23REV ! 'DIODE ZENER SINGLE SOT23_SOT23R' ! BZX84C5V1 ; D1 D6 D7 D14 D19 
SSOP20 ! 74ALS541_SSOP20_74LVC541 ! 74LVC541 ; U18 
SW_2P_6X3P5 ! 'SW KEY-SPST_SW_2P_6X3P5_RESET' ! RESET ; SW2 
SW_TH_RA_7101 ! 'SW-DPST-2P_SW_TH_RA_7101_ROCKER' ! ROCKER ; SW1 
TH_10_HDR2X5_M_STR_100 ! 'CONN 10 PIN 2MM SMT DUAL ROW_TH' ! 'CONN 10 PIN' ,
        ; J8 J9 
TH_20_HDR2X10_M_STR_100 ! 'CONN 20 PIN HP LSA_TH_20_HDR2X1' ,
        ! 'CONN 20 PIN HP LSA' ; J7 
TH_2_HDR1X2_M_STR_100 ! 'JUMPER 2X1_TH_2_HDR1X2_M_STR_10' ! 'JUMPER 2X1' ; ,
        JP1 JP2 
TH_4_HDR1X4_M_STR_100 ! 'CONN 4 PIN 0.1 SR HEADER_TH_4_H' ! 'CONN 4 PIN' ; ,
        J11 
TH_60_CON_ZPAK_HMZD_4ROW ! 'CONN 60 PIN HMZD_TH_60_CON_ZPAK' ,
        ! 'CONN 60 PIN HMZD MALE' ; U2 
TH_96_CON_ZPAK_2MM_4ROW ! FUTUREBUS_0_TH_96_CON_ZPAK_2MM_ ! FUTUREBUS_96 ; ,
        J1 
TH_LED2X2 ! LED_DUAL_PANEL_TH_LED2X2_LED_2X ! LED_2x1 ; LD8 LD9 LD10 
TO263_7P ! 'LM2676_TO263_7P_LM2676S-5.0' ! 'LM2676S-5.0' ; U13 
TO263_7P ! 'LM2676_TO263_7P_LM2676S-ADJ' ! 'LM2676S-ADJ' ; U7 U8 
TP40 ! CON1_TP40_CON1 ! CON1 ; J12 J13 J14 J15 J16 J17 J18 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM1_' ! SRAM1_CQN ; TP3 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM2_' ! SRAM2_CQ ; TP8 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM3_' ! SRAM3_CQN ; TP2 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM4_' ! SRAM4_CQ ; TP6 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM_1' ! SRAM1_CQ ; TP4 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM_2' ! SRAM3_CQ ; TP5 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM_3' ! SRAM4_CQN ; TP7 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_SRAM_4' ! SRAM2_CQN ; TP9 
TP_SMD_S35X28 ! 'TEST POINT_TP_SMD_S35X28_TP_CY_' ! TP_CY_CLK ; TP1 
'TSOT-6' ! 'LM2734 TSOT-6_TSOT-6_LM2734 TSO' ! 'LM2734 TSOT-6' ; U9 U10 U11 ,
        U12 U15 U30 
'USB-JACK-B' ! 'USB-B_0_USB-JACK-B_USB-B' ! 'USB-B' ; J4 
$NETS
10PIN_GP2 ; J8.8 R182.2 U1.AD1 
10PIN_GP3 ; J8.7 R179.2 U1.AD2 
1V2VCC_INT ; C13.1 C14.1 C15.1 C173.1 C174.1 C175.1 C176.1 C177.1 C178.1 ,
        C179.1 C180.1 L3.2 R2.2 U1.J10 U1.J11 U1.J16 U1.J17 U1.K9 U1.K10 ,
        U1.K17 U1.K18 U1.L9 U1.L10 U1.L11 U1.L16 U1.L17 U1.L18 U1.M12 ,
        U1.M15 U1.R12 U1.R15 U1.T9 U1.T10 U1.T11 U1.T16 U1.T17 U1.T18 U1.U9 ,
        U1.U10 U1.U17 U1.U18 U1.V10 U1.V11 U1.V16 U1.V17 
1V5IO ; C29.1 C82.1 C83.1 C108.1 C109.1 C110.1 C111.1 C112.1 C113.1 C114.1 ,
        C115.1 C116.1 C117.1 C118.1 C119.1 C131.1 C132.1 C133.1 C134.1 ,
        C135.1 C136.1 C141.1 C142.1 C143.1 C144.1 C145.1 C146.1 C155.1 ,
        C156.1 C157.1 C158.1 C159.1 C160.1 C165.1 C166.1 C167.1 C168.1 ,
        C169.1 C170.1 L7.2 R18.2 R57.1 R77.2 R83.2 R184.2 R185.2 R186.2 ,
        R187.2 R249.3 R250.3 R251.3 R252.3 R253.3 R254.3 R255.3 R256.3 ,
        U1.AD15 U1.AE11 U1.K8 U1.K19 U1.L2 U1.L5 U1.L22 U1.L25 U1.M18 U1.N1 ,
        U1.P26 U1.R9 U1.T2 U1.T5 U1.T22 U1.T25 U1.U8 U1.U19 U3.E4 U3.E8 ,
        U3.F4 U3.F8 U3.G4 U3.G8 U3.H3 U3.H4 U3.H8 U3.H9 U3.J4 U3.J8 U3.K4 ,
        U3.K8 U3.L4 U3.L8 U4.E4 U4.E8 U4.F4 U4.F8 U4.G4 U4.G8 U4.H3 U4.H4 ,
        U4.H8 U4.H9 U4.J4 U4.J8 U4.K4 U4.K8 U4.L4 U4.L8 U5.E4 U5.E8 U5.F4 ,
        U5.F8 U5.G4 U5.G8 U5.H3 U5.H4 U5.H8 U5.H9 U5.J4 U5.J8 U5.K4 U5.K8 ,
        U5.L4 U5.L8 U6.E4 U6.E8 U6.F4 U6.F8 U6.G4 U6.G8 U6.H3 U6.H4 U6.H8 ,
        U6.H9 U6.J4 U6.J8 U6.K4 U6.K8 U6.L4 U6.L8 U25.5 U26.5 
1V8SRAM ; C16.1 C17.1 C18.1 C127.1 C128.1 C129.1 C130.1 C137.1 C138.1 ,
        C139.1 C140.1 C151.1 C152.1 C153.1 C154.1 C161.1 C162.1 C163.1 ,
        C164.1 C208.1 C209.1 C210.1 C211.1 C212.1 C213.1 C214.1 C215.1 ,
        C216.1 C217.1 C220.1 C221.1 L4.2 R3.2 U3.F5 U3.F7 U3.G5 U3.G7 U3.H5 ,
        U3.H7 U3.J5 U3.J7 U3.K5 U3.K7 U4.F5 U4.F7 U4.G5 U4.G7 U4.H5 U4.H7 ,
        U4.J5 U4.J7 U4.K5 U4.K7 U5.F5 U5.F7 U5.G5 U5.G7 U5.H5 U5.H7 U5.J5 ,
        U5.J7 U5.K5 U5.K7 U6.F5 U6.F7 U6.G5 U6.G7 U6.H5 U6.H7 U6.J5 U6.J7 ,
        U6.K5 U6.K7 
2V5AUX ; C12.1 C122.1 C171.1 C172.1 C196.1 L2.2 R8.2 U1.AF17 U1.H11 U1.H16 ,
        U1.H17 U1.J12 U1.M9 U1.N9 U1.N18 U1.P9 U1.P18 U1.R18 U1.V15 U1.W10 ,
        U1.W11 U1.W16 U25.6 U25.7 U26.6 U26.7 
2V5IO ; C28.1 C84.1 C85.1 C86.1 C87.1 C88.1 C89.1 L6.2 R16.2 R172.1 R173.1 ,
        R174.1 R175.1 R176.1 R202.1 U1.B19 U1.B22 U1.E19 U1.F22 U1.F25 ,
        U1.H18 U1.H19 U1.J19 
3V3DUT ; C32.1 C33.1 L14.2 L16.1 L17.2 R12.2 R25.2 R283.2 R292.1 R297.1 ,
        U14.2 U14.4 U17.5 U31.5 
3V3IO ; C27.1 C48.1 C61.1 C63.1 C66.1 C74.1 C75.1 C76.1 C77.1 C78.1 C79.1 ,
        C96.1 C97.1 C98.1 C99.1 C100.1 C101.1 D8.1 J3.1 J8.4 L5.2 R14.2 ,
        R26.2 R27.2 R28.2 R29.2 R30.2 R31.2 R32.1 R33.1 R34.1 R35.1 R36.1 ,
        R37.2 R40.1 R41.1 R43.1 R44.1 R177.1 R178.1 R179.1 R180.1 R181.1 ,
        R182.1 R183.1 R193.2 R194.2 R195.2 R196.2 R197.2 R198.2 R257.2 ,
        R258.2 R259.2 R260.2 R261.2 R262.2 R271.2 R272.2 U1.AA22 U1.AA25 ,
        U1.AB11 U1.AB16 U1.AB19 U1.AE19 U1.AE22 U1.E11 U1.E16 U1.J15 U1.V12 ,
        U1.V19 U1.W17 U1.W18 U18.20 U20.1 Y1.4 
3V3USB ; C43.1 C44.1 C49.1 C50.1 C51.1 C52.1 C53.1 C54.1 C55.1 C56.1 C57.1 ,
        C64.1 C65.1 C199.1 L12.2 R45.2 R51.2 R52.2 R53.1 R279.1 U16.2 U16.4 ,
        U19.2 U19.26 U19.43 U19.48 U19.64 U19.68 U19.81 U19.100 U19.101 ,
        U19.107 U21.5 U22.8 U29.5 
3V3_2V5_IO ; C39.1 C80.1 C81.1 C90.1 C91.1 C92.1 C93.1 C94.1 C95.1 L9.2 ,
        R22.2 R60.1 R201.1 U1.B5 U1.B8 U1.B11 U1.B16 U1.E8 U1.F2 U1.F5 ,
        U1.H9 U1.H10 U1.J8 
5V ; C40.1 C41.1 C42.1 L8.2 L10.2 L13.2 R11.1 R292.3 U13.6 
5VUSB ; C45.1 C46.1 D18.2 L11.1 Q2.2 Q2.3 R295.1 
BANK1_BW01 ; R86.1 U1.M25 U3.A5 U3.B7 U4.A5 U4.B7 
BANK1_FRAME_FDBK ; R274.2 U1.AE14 
BANK1_R_WN ; R94.1 U1.R26 U3.A4 U4.A4 
BANK1_SA1 ; R108.2 U1.V23 U3.R3 U4.R3 
BANK1_SA2 ; R116.2 U1.U25 U3.R4 U4.R4 
BANK1_SA3 ; R125.2 U1.P23 U3.R5 U4.R5 
BANK1_SA4 ; R133.2 U1.N22 U3.R7 U4.R7 
BANK1_SA5 ; R141.2 U1.M23 U3.R8 U4.R8 
BANK1_SA6 ; R149.2 U1.L24 U3.R9 U4.R9 
BANK1_SA7 ; R157.2 U1.U22 U3.P4 U4.P4 
BANK1_SA8 ; R109.2 U1.T21 U3.P5 U4.P5 
BANK1_SA9 ; R117.2 U1.M22 U3.P7 U4.P7 
BANK1_SA10 ; R126.2 U1.L23 U3.P8 U4.P8 
BANK1_SA11 ; R134.2 U1.M21 U3.N5 U4.N5 
BANK1_SA12 ; R142.2 U1.L21 U3.N6 U4.N6 
BANK1_SA13 ; R150.2 U1.K21 U3.N7 U4.N7 
BANK1_SA14 ; R158.2 U1.P19 U3.C5 U4.C5 
BANK1_SA15 ; R110.2 U1.L20 U3.C7 U4.C7 
BANK1_SA16 ; R118.2 U1.R19 U3.B4 U4.B4 
BANK1_SA17 ; R127.2 U1.K20 U3.B8 U4.B8 
BANK1_SA18 ; R135.2 U1.R20 U3.A3 U4.A3 
BANK1_SA19 ; R143.2 U1.M20 U3.A9 U4.A9 
BANK1_SA20 ; R151.2 U3.A10 U4.A10 
BANK1_SA21 ; R159.2 U3.A2 U4.A2 
BANK1_SA_0 ; R219.2 U3.C6 U4.C6 
BANK2_BW01 ; R165.1 U1.R2 U5.A5 U5.B7 U6.A5 U6.B7 
BANK2_FRAME_FDBK ; R275.2 U1.AE13 
BANK2_R_WN ; R169.1 U1.M1 U5.A4 U6.A4 
BANK2_SA1 ; R112.2 U1.J2 U5.R3 U6.R3 
BANK2_SA2 ; R120.2 U1.K2 U5.R4 U6.R4 
BANK2_SA3 ; R129.2 U1.N4 U5.R5 U6.R5 
BANK2_SA4 ; R137.2 U1.R1 U5.R7 U6.R7 
BANK2_SA5 ; R145.2 U1.T3 U5.R8 U6.R8 
BANK2_SA6 ; R153.2 U1.V4 U5.R9 U6.R9 
BANK2_SA7 ; R161.2 U1.K4 U5.P4 U6.P4 
BANK2_SA8 ; R113.2 U1.M4 U5.P5 U6.P5 
BANK2_SA9 ; R121.2 U1.T4 U5.P7 U6.P7 
BANK2_SA10 ; R130.2 U1.U4 U5.P8 U6.P8 
BANK2_SA11 ; R138.2 U1.M5 U5.N5 U6.N5 
BANK2_SA12 ; R146.2 U1.N5 U5.N6 U6.N6 
BANK2_SA13 ; R154.2 U1.P5 U5.N7 U6.N7 
BANK2_SA14 ; R162.2 U1.N7 U5.C5 U6.C5 
BANK2_SA15 ; R114.2 U1.P7 U5.C7 U6.C7 
BANK2_SA16 ; R122.2 U1.M7 U5.B4 U6.B4 
BANK2_SA17 ; R131.2 U1.R7 U5.B8 U6.B8 
BANK2_SA18 ; R139.2 U1.M8 U5.A3 U6.A3 
BANK2_SA19 ; R147.2 U1.R8 U5.A9 U6.A9 
BANK2_SA20 ; R155.2 U5.A10 U6.A10 
BANK2_SA21 ; R163.2 U5.A2 U6.A2 
BANK2_SA_0 ; R229.2 U5.C6 U6.C6 
BANK8_VCCO ; C102.1 C103.1 C104.1 C105.1 C106.1 C107.1 C203.1 L18.2 R63.2 ,
        R284.2 U1.AA2 U1.AA5 U1.AB8 U1.AE5 U1.AE8 U1.V8 U1.W8 U1.W9 
BANK8_VCCO_SEL ; LD20.1 R283.1 R288.2 R289.2 U31.2 
C1A_NEG ; R249.2 U3.R6 
C1A_PLS ; R250.2 U3.P6 
C1B_NEG ; R251.2 U4.R6 
C1B_PLS ; R252.2 U4.P6 
C2A_NEG ; R253.2 U5.R6 
C2A_PLS ; R254.2 U5.P6 
C2B_NEG ; R256.2 U6.R6 
C2B_PLS ; R255.2 U6.P6 
CLK_ACTIVE ; LD2.2 LD8.3 U18.17 
CLK_REF_DCM_BYPASS ; U1.AD11 U1.AF11 
CONF_CCLK ; R42.1 R48.2 
CONF_DIN ; U1.G12 U19.78 
CONF_DONE ; R40.2 U1.H14 U19.115 
CONF_INITB ; R41.2 U1.G15 U19.79 
CS_N ; U1.W20 U19.42 
CTL0 ; J1.D8 U1.F11 
CTL1 ; J1.D7 U1.F12 
CTL2 ; J1.D6 U1.F13 
CTL3 ; J1.D5 U1.F14 
CTL4 ; J1.D4 U1.E10 
CTL5 ; J1.D3 U1.F10 
CTL6 ; J1.D2 U1.G9 
CTL7 ; J1.D1 U1.G10 
CY_ADDR0 ; U1.Y22 U19.94 
CY_ADDR1 ; U1.Y23 U19.95 
CY_ADDR2 ; U1.AA23 U19.96 
CY_ADDR3 ; U1.AA26 U19.97 
CY_ADDR4 ; U1.AB22 U19.117 
CY_ADDR5 ; U1.AB23 U19.118 
CY_ADDR6 ; U1.AB26 U19.119 
CY_ADDR7 ; U1.AC22 U19.120 
CY_ADDR8 ; U1.AC23 U19.126 
CY_ADDR9 ; U1.AC24 U19.127 
CY_ADDR10 ; U1.AC25 U19.128 
CY_ADDR11 ; U1.AC26 U19.21 
CY_ADDR12 ; U1.AD22 U19.22 
CY_ADDR13 ; U1.AD23 U19.23 
CY_ADDR14 ; U1.AD25 U19.24 
CY_ADDR15 ; U1.AD26 U19.25 
CY_CTL3 ; U1.AA20 U19.66 
CY_CTL4 ; U1.Y17 U19.67 
CY_CTL5 ; U1.AB20 U19.98 
CY_DATA0 ; U1.AC16 U19.59 
CY_DATA1 ; U1.AC15 U19.60 
CY_DATA2 ; U1.AD14 U19.61 
CY_DATA3 ; U1.AC14 U19.62 
CY_DATA4 ; U1.AB13 U19.63 
CY_DATA5 ; U1.AA13 U19.86 
CY_DATA6 ; U1.AA12 U19.87 
CY_DATA7 ; U1.AA11 U19.88 
CY_FD0 ; U1.W26 U19.44 
CY_FD1 ; U1.W25 U19.45 
CY_FD2 ; U1.W23 U19.46 
CY_FD3 ; U1.V22 U19.47 
CY_FD4 ; U1.W22 U19.54 
CY_FD5 ; U1.AE24 U19.55 
CY_FD6 ; U1.AF24 U19.56 
CY_FD7 ; U1.AE23 U19.57 
CY_FD8 ; U1.AF23 U19.102 
CY_FD9 ; U1.V21 U19.103 
CY_FD10 ; U1.W21 U19.104 
CY_FD11 ; U1.Y20 U19.105 
CY_FD12 ; U1.W19 U19.121 
CY_FD13 ; U1.Y19 U19.122 
CY_FD14 ; U1.Y18 U19.123 
CY_FD15 ; U1.AA18 U19.124 
CY_ID0 ; R289.1 U1.D16 U19.72 
CY_ID1 ; R294.1 U1.E14 U19.73 
CY_ID2 ; U1.D14 U19.74 
CY_ID3 ; U1.D11 U19.75 
CY_REQ ; R39.2 U1.AC19 
CY_VALID ; U1.AA19 U19.114 
DATA_CLK_FB ; J1.D23 U1.C13 
DATA_IN1 ; J1.B20 U1.B9 
DATA_IN2 ; J1.B19 U1.A7 
DATA_IN3 ; J1.B18 U1.C7 
DATA_IN4 ; J1.B17 U1.A5 
DATA_IN5 ; J1.B16 U1.B4 
DATA_IN6 ; J1.B15 U1.B3 
DATA_IN7 ; J1.B14 U1.C1 
DATA_IN8 ; J1.B13 U1.D1 
DATA_IN10 ; J1.B11 U1.E4 
DATA_IN11 ; J1.B10 U1.E2 
DATA_IN12 ; J1.B9 U1.F1 
DATA_IN13 ; J1.B8 U1.G3 
DATA_IN14 ; J1.B7 U1.G1 
DATA_IN15 ; J1.B6 U1.H3 
DATA_IN16 ; J1.B5 U1.H1 
DATA_IN17 ; J1.B4 U1.C10 
DATA_IN19 ; J1.A20 U1.A9 
DATA_IN20 ; J1.A19 U1.A8 
DATA_IN21 ; J1.A18 U1.B7 
DATA_IN22 ; J1.A17 U1.A6 
DATA_IN23 ; J1.A16 U1.A4 
DATA_IN24 ; J1.A15 U1.A3 
DATA_IN25 ; J1.A14 U1.C2 
DATA_IN26 ; J1.A13 U1.D2 
DATA_IN28 ; J1.A11 U1.D3 
DATA_IN29 ; J1.A10 U1.E3 
DATA_IN30 ; J1.A9 U1.E1 
DATA_IN31 ; J1.A8 U1.G4 
DATA_IN32 ; J1.A7 U1.G2 
DATA_IN33 ; J1.A6 U1.H4 
DATA_IN34 ; J1.A5 U1.H2 
DATA_IN35 ; J1.A4 U1.D10 
DATA_IN37 ; U1.A22 U2.D2 
DATA_IN38 ; U1.A24 U2.D3 
DATA_IN41 ; U1.E25 U2.D6 
DATA_IN42 ; U1.F26 U2.D7 
DATA_IN43 ; U1.G26 U2.D8 
DATA_IN44 ; U1.G24 U2.D9 
DATA_IN47 ; U1.A21 U2.E2 
DATA_IN48 ; U1.A23 U2.E3 
DATA_IN51 ; U1.E24 U2.E6 
DATA_IN52 ; U1.E26 U2.E7 
DATA_IN53 ; U1.G25 U2.E8 
DATA_IN54 ; U1.G23 U2.E9 
DATA_IN56 ; U1.A20 U2.A1 
DATA_IN57 ; U1.C21 U2.A2 
DATA_IN58 ; U1.B24 U2.A3 
DATA_IN59 ; U1.D24 U2.A4 
DATA_IN60 ; U1.C26 U2.A5 
DATA_IN61 ; U1.D26 U2.A6 
DATA_IN62 ; U1.A19 U2.B1 
DATA_IN63 ; U1.B21 U2.B2 
DATA_IN64 ; U1.B23 U2.B3 
DATA_IN65 ; U1.C24 U2.B4 
DATA_IN66 ; U1.C25 U2.B5 
DATA_IN67 ; U1.D25 U2.B6 
DATA_IN0_CLK ; J1.B21 U1.B12 
DATA_IN18_CLK ; J1.A21 U1.B13 
DATA_IN27_CLK ; J1.A12 U1.C15 
DATA_IN36_CLK ; U1.A10 U2.D1 
DATA_IN39_CLK ; U1.B15 U2.D4 
DATA_IN40_CLK ; U1.A16 U2.D5 
DATA_IN45_CLK ; U1.B17 U2.D10 
DATA_IN46_CLK ; U1.B10 U2.E1 
DATA_IN49_CLK ; U1.B14 U2.E4 
DATA_IN50_CLK ; U1.A15 U2.E5 
DATA_IN55_CLK ; U1.A17 U2.E10 
DATA_IN9_CLK ; J1.B12 U1.C14 
DUT_VCCO_SEL ; LD19.1 R25.1 R47.2 R279.2 R280.2 U17.2 U29.2 
EXP_CLK_N ; J5.5 JP21.1 U1.W1 
EXP_CLK_P ; J5.6 JP22.1 U1.W2 
EXP_DATA_N0 ; J5.37 JP5.1 U1.AF7 
EXP_DATA_N1 ; J5.35 JP7.1 U1.Y8 
EXP_DATA_N2 ; J5.33 JP9.1 U1.AA10 
EXP_DATA_N3 ; J5.31 JP11.1 U1.AB7 
EXP_DATA_N4 ; J5.29 JP13.1 U1.AB9 
EXP_DATA_N5 ; J5.27 JP15.1 U1.AD6 
EXP_DATA_N6 ; J5.25 JP17.1 U1.AE9 
EXP_DATA_N7 ; J5.23 JP19.1 U1.AC8 
EXP_DATA_N8 ; J5.21 JP23.1 U1.AE4 
EXP_DATA_N9 ; J5.19 JP25.1 U1.AC3 
EXP_DATA_N10 ; J5.17 JP27.1 U1.AF5 
EXP_DATA_N11 ; J5.15 JP29.1 U1.Y7 
EXP_DATA_N12 ; J5.13 JP31.1 U1.Y9 
EXP_DATA_N13 ; J5.11 JP33.1 U1.AD4 
EXP_DATA_N14 ; J5.9 JP35.1 U1.V7 
EXP_DATA_N15 ; J5.7 JP37.1 U1.V5 
EXP_DATA_P0 ; J5.38 JP6.1 U1.AF8 
EXP_DATA_P1 ; J5.36 JP8.1 U1.AA8 
EXP_DATA_P2 ; J5.34 JP10.1 U1.Y10 
EXP_DATA_P3 ; J5.32 JP12.1 U1.AC7 
EXP_DATA_P4 ; J5.30 JP14.1 U1.AC9 
EXP_DATA_P5 ; J5.28 JP16.1 U1.AE6 
EXP_DATA_P6 ; J5.26 JP18.1 U1.AF9 
EXP_DATA_P7 ; J5.24 JP20.1 U1.AD8 
EXP_DATA_P8 ; J5.22 JP24.1 U1.AF4 
EXP_DATA_P9 ; J5.20 JP26.1 U1.AD3 
EXP_DATA_P10 ; J5.18 JP28.1 U1.AF6 
EXP_DATA_P11 ; J5.16 JP30.1 U1.AA7 
EXP_DATA_P12 ; J5.14 JP32.1 U1.AA9 
EXP_DATA_P13 ; J5.12 JP34.1 U1.AD5 
EXP_DATA_P14 ; J5.10 JP36.1 U1.W7 
EXP_DATA_P15 ; J5.8 JP38.1 U1.V6 
FIFOADR0 ; U1.AD21 U19.89 
FIFOADR1 ; U1.AE21 U19.90 
FLAGA ; U1.AE18 U19.69 
FLAGB ; U1.W24 U19.70 
FLAGC ; U1.Y21 U19.71 
FPGA_RESET ; R45.1 R46.2 U1.AB25 
GND ; C1.2 C2.2 C4.2 C5.2 C6.2 C7.2 C9.2 C10.2 C12.2 C13.2 C14.2 C15.2 ,
        C16.2 C17.2 C18.2 C19.2 C20.2 C21.2 C22.2 C23.2 C27.2 C28.2 C29.2 ,
        C30.2 C31.2 C32.2 C33.2 C34.2 C36.2 C37.2 C39.2 C40.2 C41.2 C42.2 ,
        C43.2 C44.2 C45.2 C46.2 C47.2 C48.2 C49.2 C50.2 C51.2 C52.2 C53.2 ,
        C54.2 C55.2 C56.2 C57.2 C58.2 C59.2 C60.2 C61.2 C63.2 C64.2 C65.2 ,
        C66.2 C67.1 C68.2 C69.2 C74.2 C75.2 C76.2 C77.2 C78.2 C79.2 C80.2 ,
        C81.2 C82.2 C83.2 C84.2 C85.2 C86.2 C87.2 C88.2 C89.2 C90.2 C91.2 ,
        C92.2 C93.2 C94.2 C95.2 C96.2 C97.2 C98.2 C99.2 C100.2 C101.2 ,
        C102.2 C103.2 C104.2 C105.2 C106.2 C107.2 C108.2 C109.2 C110.2 ,
        C111.2 C112.2 C113.2 C114.2 C115.2 C116.2 C117.2 C118.2 C119.2 ,
        C120.2 C121.2 C122.2 C123.2 C124.2 C125.2 C126.2 C127.2 C128.2 ,
        C129.2 C130.2 C131.2 C132.2 C133.2 C134.2 C135.2 C136.2 C137.2 ,
        C138.2 C139.2 C140.2 C141.2 C142.2 C143.2 C144.2 C145.2 C146.2 ,
        C147.2 C148.2 C149.2 C150.2 C151.2 C152.2 C153.2 C154.2 C155.2 ,
        C156.2 C157.2 C158.2 C159.2 C160.2 C161.2 C162.2 C163.2 C164.2 ,
        C165.2 C166.2 C167.2 C168.2 C169.2 C170.2 C171.2 C172.2 C173.2 ,
        C174.2 C175.2 C176.2 C177.2 C178.2 C179.2 C180.2 C186.2 C187.2 ,
        C188.2 C189.2 C190.2 C191.2 C192.2 C193.2 C194.2 C195.2 C196.2 ,
        C197.2 C198.2 C199.2 C200.2 C201.2 C203.2 C204.2 C205.2 C206.2 ,
        C207.2 C208.2 C209.2 C210.2 C211.2 C212.2 C213.2 C214.2 C215.2 ,
        C216.2 C217.2 C220.2 C221.2 C240.2 D1.3 D3.1 D4.1 D5.1 D6.3 D7.3 ,
        D11.1 D12.1 D13.1 D14.3 D16.1 D17.1 D18.1 D19.3 D21.1 J1.A3 J1.A22 ,
        J1.B3 J1.C1 J1.C2 J1.C3 J1.C4 J1.C5 J1.C6 J1.C7 J1.C8 J1.C9 J1.C10 ,
        J1.C11 J1.C12 J1.C13 J1.C14 J1.C15 J1.C16 J1.C17 J1.C18 J1.C19 ,
        J1.C20 J1.C21 J1.C23 J1.C24 J1.D9 J1.D14 J1.D21 J1.D24 J3.6 J4.4 ,
        J5.3 J5.39 J5.40 J5.41 J5.42 J5.43 J7.20 J8.2 J9.2 J9.4 J9.6 J9.8 ,
        J9.10 J10.A3 J10.A6 J10.A9 J10.A12 J10.A14 J10.A17 J10.A20 J10.A23 ,
        J10.A26 J10.B3 J10.B6 J10.B9 J10.B12 J10.B14 J10.B17 J10.B20 ,
        J10.B23 J10.B26 J12.1 J13.1 J14.1 J15.1 J16.1 J17.1 J18.1 L1.3 ,
        LD1.2 LD6.2 LD8.4 Q1.2 Q3.2 R5.1 R6.1 R7.1 R13.1 R15.1 R17.1 R20.1 ,
        R23.1 R43.3 R44.3 R49.1 R50.1 R53.3 R54.2 R56.1 R58.2 R59.2 R64.2 ,
        R65.2 R70.2 R84.1 R88.1 R89.1 R90.1 R105.2 R124.1 R151.1 R152.1 ,
        R155.1 R156.1 R159.1 R163.1 R199.1 R200.1 R217.1 R219.1 R227.1 ,
        R229.1 R238.1 R247.1 R263.1 R264.1 R265.1 R266.1 R267.1 R268.1 ,
        R269.1 R270.1 R280.1 R281.1 R286.1 R287.1 R288.1 R290.1 R291.2 ,
        R293.2 R298.1 SW2.2 U1.A2 U1.A13 U1.A14 U1.A25 U1.AA6 U1.AA21 ,
        U1.AB12 U1.AB15 U1.AD9 U1.AD18 U1.AD24 U1.AE1 U1.AE2 U1.AE15 ,
        U1.AE16 U1.AE17 U1.AE25 U1.AE26 U1.AF2 U1.AF13 U1.AF14 U1.AF15 ,
        U1.AF16 U1.AF25 U1.B1 U1.B2 U1.B25 U1.B26 U1.C3 U1.C9 U1.C18 U1.E12 ,
        U1.E15 U1.F6 U1.F21 U1.J3 U1.J13 U1.J14 U1.J24 U1.K11 U1.K12 U1.K13 ,
        U1.K14 U1.K15 U1.K16 U1.L12 U1.L13 U1.L14 U1.L15 U1.M10 U1.M11 ,
        U1.M13 U1.M14 U1.M16 U1.M17 U1.N6 U1.N10 U1.N11 U1.N12 U1.N13 ,
        U1.N14 U1.N15 U1.N16 U1.N17 U1.N26 U1.P1 U1.P10 U1.P11 U1.P12 ,
        U1.P13 U1.P14 U1.P15 U1.P16 U1.P17 U1.P21 U1.R10 U1.R11 U1.R13 ,
        U1.R14 U1.R16 U1.R17 U1.T12 U1.T13 U1.T14 U1.T15 U1.U11 U1.U12 ,
        U1.U13 U1.U14 U1.U15 U1.U16 U1.V3 U1.V13 U1.V14 U1.V24 U1.Y16 U2.C1 ,
        U2.C2 U2.C3 U2.C4 U2.C5 U2.C6 U2.C7 U2.C8 U2.C9 U2.C10 U2.F1 U2.F2 ,
        U2.F3 U2.F4 U2.F5 U2.F6 U2.F7 U2.F8 U2.F9 U2.F10 U3.C4 U3.C8 U3.D4 ,
        U3.D5 U3.D6 U3.D7 U3.D8 U3.E5 U3.E6 U3.E7 U3.F6 U3.G6 U3.H6 U3.J6 ,
        U3.K6 U3.L5 U3.L6 U3.L7 U3.M4 U3.M5 U3.M6 U3.M7 U3.M8 U3.N4 U3.N8 ,
        U4.C4 U4.C8 U4.D4 U4.D5 U4.D6 U4.D7 U4.D8 U4.E5 U4.E6 U4.E7 U4.F6 ,
        U4.G6 U4.H6 U4.J6 U4.K6 U4.L5 U4.L6 U4.L7 U4.M4 U4.M5 U4.M6 U4.M7 ,
        U4.M8 U4.N4 U4.N8 U5.C4 U5.C8 U5.D4 U5.D5 U5.D6 U5.D7 U5.D8 U5.E5 ,
        U5.E6 U5.E7 U5.F6 U5.G6 U5.H6 U5.J6 U5.K6 U5.L5 U5.L6 U5.L7 U5.M4 ,
        U5.M5 U5.M6 U5.M7 U5.M8 U5.N4 U5.N8 U6.C4 U6.C8 U6.D4 U6.D5 U6.D6 ,
        U6.D7 U6.D8 U6.E5 U6.E6 U6.E7 U6.F6 U6.G6 U6.H6 U6.J6 U6.K6 U6.L5 ,
        U6.L6 U6.L7 U6.M4 U6.M5 U6.M6 U6.M7 U6.M8 U6.N4 U6.N8 U7.4 U8.4 ,
        U9.2 U10.2 U11.2 U12.2 U13.4 U14.1 U15.2 U16.1 U17.3 U18.1 U18.2 ,
        U18.8 U18.9 U18.10 U18.19 U19.3 U19.13 U19.20 U19.27 U19.33 U19.49 ,
        U19.58 U19.65 U19.80 U19.93 U19.116 U19.125 U20.4 U20.5 U20.6 U21.1 ,
        U21.2 U22.2 U22.3 U22.4 U22.7 U25.1 U26.1 U29.3 U30.2 U31.3 Y1.2 
GP0 ; U1.C11 U2.B7 
GP1 ; U1.D12 U2.B8 
GP2 ; U1.D15 U2.B9 
GP3 ; U1.C16 U2.B10 
GP4 ; J1.D20 U1.B6 
GP5 ; J1.D19 U1.C6 
GP6 ; J1.D18 U1.D6 
GP7 ; J1.D17 U1.C8 
GP8 ; J1.D16 U1.D7 
GP9 ; J1.D15 U1.D8 
HP_CLK ; J7.3 U1.AC1 
HP_DATA0 ; J7.19 U1.Y2 
HP_DATA1 ; J7.18 U1.Y1 
HP_DATA2 ; J7.17 U1.AA4 
HP_DATA3 ; J7.16 U1.AA3 
HP_DATA4 ; J7.15 U1.Y4 
HP_DATA5 ; J7.14 U1.Y3 
HP_DATA6 ; J7.13 U1.Y6 
HP_DATA7 ; J7.12 U1.Y5 
HP_DATA8 ; J7.11 U1.AB1 
HP_DATA9 ; J7.10 U1.AA1 
HP_DATA10 ; J7.9 U1.AC4 
HP_DATA11 ; J7.8 U1.AB4 
HP_DATA12 ; J7.7 U1.AB3 
HP_DATA13 ; J7.6 U1.AB2 
HP_DATA14 ; J7.5 U1.AC5 
HP_DATA15 ; J7.4 U1.AB5 
ID0 ; J1.D13 U1.H7 
ID1 ; J1.D12 U1.H8 
ID2 ; J1.D11 U1.F15 
ID3 ; J1.D10 U1.F16 
IDLE ; LD4.2 LD9.4 U18.16 
IFCLK ; R276.2 U19.32 
IFCLK_BIDIR ; R277.1 U1.D13 
IFCLK_OUT ; R276.1 R278.2 U1.C12 
JP_1 ; J9.1 R176.2 U1.D21 
JP_2 ; J9.3 R175.2 U1.C22 
JP_3 ; J9.5 R174.2 U1.D22 
JP_4 ; J9.7 R173.2 U1.C23 
JP_5 ; J9.9 R172.2 U1.D23 
K1_NEG ; R98.1 R249.1 R251.1 U1.AC17 U1.N24 U3.A6 U4.A6 
K1_PLS ; R97.1 R250.1 R252.1 U1.AB17 U1.N25 U3.B6 U4.B6 
K2_NEG ; R171.1 R253.1 R256.1 U1.AB10 U1.P2 U5.A6 U6.A6 
K2_PLS ; R170.1 R254.1 R255.1 U1.AC10 U1.P3 U5.B6 U6.B6 
LED_CLK_ACTIVE ; R36.2 U1.AC11 U18.3 
LED_DCM0 ; LD17.2 R270.2 U1.H26 
LED_DCM1 ; LD15.2 R269.2 U1.H25 
LED_DCM2 ; LD13.2 R268.2 U1.H24 
LED_DCM3 ; LD11.2 R267.2 U1.H23 
LED_DCM4 ; LD18.2 R266.2 U1.H22 
LED_DCM5 ; LD16.2 R265.2 U1.F24 
LED_DCM6 ; LD14.2 R264.2 U1.F23 
LED_DCM7 ; LD12.2 R263.2 U1.E23 
LED_IDLE ; R35.2 U1.AC12 U18.4 
LED_OVERRANGE ; R34.2 U1.AA16 U18.5 
LED_SAMPLE ; R32.2 U1.AA14 U18.7 
LED_UPLOAD ; R33.2 U1.AB14 U18.6 
LN_N ; J11.2 U1.AC6 
LN_P ; J11.4 U1.AF3 
LOAD_STATE ; R38.2 U1.AF18 
N16721567 ; J4.3 U19.18 
N16721659 ; J4.2 U19.19 
N16722721 ; C67.2 J4.5 J4.6 R56.2 
N16727306 ; R54.1 U19.35 
N16728417 ; JP2.2 R51.1 R248.2 U19.37 
N16784821 ; C2.1 D1.1 D2.1 R1.2 
N16784934 ; L1.4 SW1.3 
N16785129 ; LD1.1 R4.2 
N16785233 ; R4.1 R168.1 SW1.2 
N16785324 ; Q1.1 R19.2 R20.2 
N16785561 ; J2.1 L1.1 
N16785565 ; J2.2 L1.2 
N16785881 ; JP1.1 R11.2 R273.2 U7.7 U8.7 U9.4 U10.4 U11.4 U12.4 U15.4 U30.4 
N16785887 ; R7.2 R8.1 U9.3 
N16786195 ; C3.2 D3.2 L2.1 U9.6 
N16786312 ; C3.1 D2.2 U9.1 
N16790515 ; C47.1 L11.2 U16.3 
N17041129 ; R50.2 U19.99 U21.3 
N17055879 ; R49.2 U1.AD20 
N17055981 ; R37.1 U1.AE20 
N17108969 ; R63.1 U1.AE7 
N17109039 ; R64.1 U1.AD7 
N17121014 ; C58.1 C59.1 C60.1 L12.1 U19.10 U19.17 
N17122999 ; R53.2 U22.1 
N17127467 ; R46.1 U19.85 
N17135258 ; JP1.2 Q1.3 R273.1 
N17182080 ; R44.2 U1.G16 
N17182183 ; C62.1 U1.H13 U20.2 
N17182215 ; C62.2 U1.G13 U20.3 
N17182407 ; R42.2 U1.G14 
N17182422 ; R43.2 U1.W14 U1.W15 U1.Y15 
N17189786 ; R47.1 U19.82 
N17193122 ; R58.1 U1.AD16 
N17193152 ; R57.2 U1.AD17 
N17223723 ; C8.1 D4.2 L3.1 U7.1 
N17223731 ; C8.2 U7.3 
N17223745 ; R2.1 R5.2 U7.6 
N17228694 ; C11.1 D5.2 L4.1 U8.1 
N17228718 ; C11.2 U8.3 
N17228734 ; R3.1 R6.2 U8.6 
N17231729 ; C24.2 D11.2 L5.1 U10.6 
N17231793 ; R13.2 R14.1 U10.3 
N17231837 ; C24.1 D8.2 U10.1 
N17234632 ; C25.2 D12.2 L6.1 U11.6 
N17234708 ; R15.2 R16.1 U11.3 
N17234750 ; C22.1 D6.1 D9.1 R9.2 
N17234762 ; C25.1 D9.2 U11.1 
N17258918 ; C38.1 D17.2 L10.1 U13.1 
N17258932 ; C38.2 U13.3 
N17264627 ; C34.1 L8.1 U14.3 
N17278098 ; C26.2 D13.2 L7.1 U12.6 
N17278176 ; R17.2 R18.1 U12.3 
N17278202 ; C23.1 D7.1 D10.1 R10.2 
N17278222 ; C26.1 D10.2 U12.1 
N17280725 ; C35.2 D16.2 L9.1 U15.6 
N17280803 ; R22.1 R23.2 R24.2 U15.3 
N17280829 ; C31.1 D14.1 D15.1 R21.2 
N17280849 ; C35.1 D15.2 U15.1 
N17285435 ; R24.1 U17.4 
N17300265 ; R77.1 U1.R6 
N17300273 ; R90.2 U1.R5 
N17300278 ; R84.2 U1.R21 
N17300280 ; R83.1 U1.R22 
N17301402 ; R185.1 U3.H1 
N17306796 ; L14.1 U2.A9 U2.A10 
N17307225 ; J1.A1 J1.A2 J1.B1 J1.B2 L16.2 
N17307246 ; J1.A23 J1.A24 J1.B23 J1.B24 L13.1 
N17308233 ; J1.D22 L17.1 
N17309707 ; R65.1 U5.H11 
N17309857 ; R70.1 U3.H11 
N17321679 ; R59.1 U1.A11 
N17321693 ; R60.2 U1.A12 
N17383940 ; C68.1 U19.11 Y2.1 
N17383990 ; C69.1 U19.12 Y2.2 
N17384219 ; TP1.1 U19.1 
N17414023 ; SW2.1 U21.4 
N17458107 ; J8.10 R183.2 
N17462280 ; R186.1 U6.H1 
N17462381 ; R184.1 U5.H1 
N17462614 ; R187.1 U4.H1 
N17853901 ; LD8.1 R193.1 
N17853925 ; LD8.2 R194.1 
N17853999 ; LD9.1 R195.1 
N17854001 ; LD9.2 R196.1 
N17854003 ; LD10.1 R197.1 
N17854005 ; LD10.2 R198.1 
N18048558 ; R201.2 U1.G6 
N18048572 ; R199.2 U1.G5 
N18049603 ; R200.2 U1.G21 
N18049617 ; R202.2 U1.G22 
N18092594 ; R39.1 U19.113 
N18092628 ; R38.1 U19.112 
N18102458 ; R48.1 U19.77 
N18969935 ; R55.1 Y1.3 
N18969971 ; R55.2 R291.1 U1.AD12 
N19046349 ; R105.1 U6.H11 
N19294394 ; R275.1 U1.N3 
N19373343 ; R274.1 U1.P24 
N19393569 ; TP5.1 U5.A11 
N19393654 ; TP2.1 U5.A1 
N19394019 ; TP6.1 U6.A11 
N19394086 ; TP7.1 U6.A1 
N19394229 ; TP9.1 U4.A1 
N19394296 ; TP8.1 U4.A11 
N19394463 ; TP3.1 U3.A1 
N19394530 ; TP4.1 U3.A11 
N19397246 ; R278.1 U29.4 
N19397543 ; R276.3 R277.2 
N19407774 ; LD19.2 R281.2 
N19422668 ; LD20.2 R287.2 
N19422816 ; R285.1 U31.4 
N19423069 ; R284.1 R285.2 R286.2 U30.3 
N19423073 ; C201.1 D19.1 D20.1 R282.2 
N19423103 ; C202.2 D21.2 L18.1 U30.6 
N19423126 ; C202.1 D20.2 U30.1 
N19791931 ; Q3.1 R297.2 R298.2 
N19793237 ; Q2.1 Q3.3 R296.1 
N178597020 ; LD6.1 R30.1 
N178597260 ; LD3.1 R27.1 
N178597380 ; LD5.1 R29.1 
N178597500 ; LD2.1 R26.1 
N178597620 ; LD4.1 R28.1 
N178597860 ; LD7.1 R31.1 
N182929931 ; R124.2 U4.H11 
N193215990 ; LD15.1 R261.1 
N193216110 ; LD18.1 R272.1 
N193216230 ; LD13.1 R259.1 
N193216610 ; LD14.1 R260.1 
N193217070 ; LD16.1 R262.1 
N193238060 ; LD12.1 R258.1 
N193238320 ; LD11.1 R257.1 
N193240780 ; LD17.1 R271.1 
NPOWER_EN ; R12.1 R19.1 U19.83 
OVERRANGE ; LD3.2 LD9.3 U18.15 
PKTEND ; U1.AF19 U19.91 
PROGRAMB ; U1.H15 U19.76 
PWR_DETECT ; C240.1 R292.2 R293.1 R294.2 
RD_N ; U1.Y25 U19.40 
SAMPLE ; LD7.2 LD10.3 U18.13 
SCL_FROM_CY ; J1.C22 R52.1 U2.A8 U19.36 U20.8 U22.6 
SDA_FROM_CY ; J1.B22 JP2.1 R248.1 U2.A7 U20.7 U22.5 
SLCS_N ; R290.2 U1.AA17 U19.92 
SLOE ; U1.AF20 U19.84 
SLRD ; U1.AC21 U19.4 
SLWR ; U1.AB21 U19.5 
SPI_CLK ; J8.1 R177.2 U1.AB6 
SPI_CS ; J8.5 R178.2 U1.W3 
SPI_MISO ; J8.3 U1.W4 
SPI_MOSI ; J8.9 R180.2 U1.AE3 
SPI_SEL ; J8.6 R181.2 U1.AC2 
SRAM1_DQ0 ; R92.2 U1.J26 U3.P11 
SRAM1_DQ1 ; R210.2 U1.M24 U3.M10 
SRAM1_DQ2 ; R67.2 U1.K24 U3.L11 
SRAM1_DQ3 ; R211.2 U1.J23 U3.K11 
SRAM1_DQ4 ; R69.2 U1.K23 U3.J10 
SRAM1_DQ5 ; R212.2 U1.J20 U3.F11 
SRAM1_DQ6 ; R72.2 U1.J22 U3.E11 
SRAM1_DQ7 ; R213.2 U1.K22 U3.C10 
SRAM1_DQ8 ; R74.2 U1.J21 U3.B11 
SRAM1_DQ9 ; R214.2 U1.K25 U3.B2 
SRAM1_DQ10 ; R215.2 U1.K26 U3.D3 
SRAM1_DQ11 ; R76.2 U1.N20 U3.E3 
SRAM1_DQ12 ; R216.2 U1.M19 U3.F2 
SRAM1_DQ13 ; R81.2 U1.N21 U3.G3 
SRAM1_DQ14 ; R218.2 U1.L19 U3.K3 
SRAM1_DQ15 ; R85.2 U1.N23 U3.L2 
SRAM1_DQ16 ; R217.2 U3.N3 
SRAM1_DQ17 ; R89.2 U3.P3 
SRAM1_LD ; R101.1 U1.L26 U3.A8 
SRAM2_DQ0 ; R160.2 U1.T26 U4.P11 
SRAM2_DQ1 ; R220.2 U1.U26 U4.M10 
SRAM2_DQ2 ; R103.2 U1.R24 U4.L11 
SRAM2_DQ3 ; R221.2 U1.T24 U4.K11 
SRAM2_DQ4 ; R106.2 U1.R23 U4.J10 
SRAM2_DQ5 ; R222.2 U1.T23 U4.F11 
SRAM2_DQ6 ; R111.2 U1.P22 U4.E11 
SRAM2_DQ7 ; R223.2 U1.N19 U4.C10 
SRAM2_DQ8 ; R119.2 U1.P20 U4.B11 
SRAM2_DQ9 ; R224.2 U1.T19 U4.B2 
SRAM2_DQ10 ; R225.2 U1.T20 U4.D3 
SRAM2_DQ11 ; R128.2 U1.U20 U4.E3 
SRAM2_DQ12 ; R226.2 U1.V25 U4.F2 
SRAM2_DQ13 ; R136.2 U1.U21 U4.G3 
SRAM2_DQ14 ; R228.2 U1.V26 U4.K3 
SRAM2_DQ15 ; R144.2 U1.U23 U4.L2 
SRAM2_DQ16 ; R227.2 U4.N3 
SRAM2_DQ17 ; R152.2 U4.P3 
SRAM2_LD ; R87.1 U1.P25 U4.A8 
SRAM3_DQ0 ; R91.2 U1.L1 U5.P11 
SRAM3_DQ1 ; R230.2 U1.K1 U5.M10 
SRAM3_DQ2 ; R66.2 U1.M2 U5.L11 
SRAM3_DQ3 ; R231.2 U1.K3 U5.K11 
SRAM3_DQ4 ; R68.2 U1.K6 U5.J10 
SRAM3_DQ5 ; R232.2 U1.K5 U5.F11 
SRAM3_DQ6 ; R71.2 U1.M6 U5.E11 
SRAM3_DQ7 ; R233.2 U1.K7 U5.C10 
SRAM3_DQ8 ; R73.2 U1.L7 U5.B11 
SRAM3_DQ9 ; R234.2 U1.L6 U5.B2 
SRAM3_DQ10 ; R235.2 U1.L4 U5.D3 
SRAM3_DQ11 ; R75.2 U1.J6 U5.E3 
SRAM3_DQ12 ; R236.2 U1.L3 U5.F2 
SRAM3_DQ13 ; R78.2 U1.J5 U5.G3 
SRAM3_DQ14 ; R237.2 U1.J7 U5.K3 
SRAM3_DQ15 ; R82.2 U1.J4 U5.L2 
SRAM3_DQ16 ; R238.2 U5.N3 
SRAM3_DQ17 ; R88.2 U5.P3 
SRAM3_LD ; R167.1 U1.N2 U5.A8 
SRAM4_DQ0 ; R164.2 U1.V1 U6.P11 
SRAM4_DQ1 ; R239.2 U1.R4 U6.M10 
SRAM4_DQ2 ; R104.2 U1.V2 U6.L11 
SRAM4_DQ3 ; R240.2 U1.U7 U6.K11 
SRAM4_DQ4 ; R107.2 U1.U3 U6.J10 
SRAM4_DQ5 ; R241.2 U1.T7 U6.F11 
SRAM4_DQ6 ; R115.2 U1.U5 U6.E11 
SRAM4_DQ7 ; R242.2 U1.T8 U6.C10 
SRAM4_DQ8 ; R123.2 U1.U6 U6.B11 
SRAM4_DQ9 ; R243.2 U1.N8 U6.B2 
SRAM4_DQ10 ; R244.2 U1.L8 U6.D3 
SRAM4_DQ11 ; R132.2 U1.P8 U6.E3 
SRAM4_DQ12 ; R245.2 U1.T1 U6.F2 
SRAM4_DQ13 ; R140.2 U1.P6 U6.G3 
SRAM4_DQ14 ; R246.2 U1.U1 U6.K3 
SRAM4_DQ15 ; R148.2 U1.P4 U6.L2 
SRAM4_DQ16 ; R247.2 U6.N3 
SRAM4_DQ17 ; R156.2 U6.P3 
SRAM4_LD ; R166.1 U1.T6 U6.A8 
STATE0 ; U1.AC18 U19.108 
STATE1 ; U1.AB18 U19.109 
STATE2 ; U1.AF21 U19.110 
STATE3 ; U1.AF22 U19.111 
STOUCH_N0 ; J10.A1 JP5.2 
STOUCH_N1 ; J10.A2 JP7.2 
STOUCH_N2 ; J10.A4 JP9.2 
STOUCH_N3 ; J10.A5 JP11.2 
STOUCH_N4 ; J10.A7 JP13.2 
STOUCH_N5 ; J10.A8 JP15.2 
STOUCH_N6 ; J10.A10 JP17.2 
STOUCH_N7 ; J10.A11 JP19.2 
STOUCH_N8 ; J10.A15 JP23.2 
STOUCH_N9 ; J10.A16 JP25.2 
STOUCH_N10 ; J10.A18 JP27.2 
STOUCH_N11 ; J10.A19 JP29.2 
STOUCH_N12 ; J10.A21 JP31.2 
STOUCH_N13 ; J10.A22 JP33.2 
STOUCH_N14 ; J10.A24 JP35.2 
STOUCH_N15 ; J10.A25 JP37.2 
STOUCH_NCLK ; J10.A13 JP21.2 
STOUCH_P0 ; J10.B1 JP6.2 
STOUCH_P1 ; J10.B2 JP8.2 
STOUCH_P2 ; J10.B4 JP10.2 
STOUCH_P3 ; J10.B5 JP12.2 
STOUCH_P4 ; J10.B7 JP14.2 
STOUCH_P5 ; J10.B8 JP16.2 
STOUCH_P6 ; J10.B10 JP18.2 
STOUCH_P7 ; J10.B11 JP20.2 
STOUCH_P8 ; J10.B15 JP24.2 
STOUCH_P9 ; J10.B16 JP26.2 
STOUCH_P10 ; J10.B18 JP28.2 
STOUCH_P11 ; J10.B19 JP30.2 
STOUCH_P12 ; J10.B21 JP32.2 
STOUCH_P13 ; J10.B22 JP34.2 
STOUCH_P14 ; J10.B24 JP36.2 
STOUCH_P15 ; J10.B25 JP38.2 
STOUCH_PCLK ; J10.B13 JP22.2 
TEST1N ; R192.1 U1.D17 U27.3 
TEST1P ; R192.2 U1.C17 U27.1 
TEST2N ; R191.1 U1.A18 U27.7 
TEST2P ; R191.2 U1.B18 U27.5 
TEST3N ; R190.1 U1.D18 U28.3 
TEST3P ; R190.2 U1.C19 U28.1 
TEST4N ; R189.1 U1.B20 U28.7 
TEST4P ; R189.2 U1.C20 U28.5 
UPLOAD ; LD5.2 LD10.4 U18.14 
USB_POWER ; J4.1 Q2.4 R295.2 R296.2 
V4_TCK ; J3.4 U1.W12 
V4_TDI ; J3.5 U1.Y12 
V4_TDO ; J3.3 U1.Y13 
V4_TMS ; J3.2 U1.Y11 
VIN ; C1.1 C4.1 C5.1 C6.1 C7.1 C9.1 C10.1 C19.1 C20.1 C21.1 C30.1 C36.1 ,
        C37.1 C200.1 R1.1 R9.1 R10.1 R21.1 R168.2 R282.1 U7.2 U8.2 U9.5 ,
        U10.5 U11.5 U12.5 U13.2 U15.5 U30.5 
VLD_N ; J11.1 U1.W6 
VLD_P ; J11.3 U1.W5 
VREF_3_4 ; C120.1 C123.1 C124.1 C147.1 C148.1 C190.1 C191.1 C192.1 C193.1 ,
        U1.J25 U1.M26 U1.R25 U1.U24 U3.H2 U3.H10 U4.H2 U4.H10 U25.4 
VREF_5_6 ; C125.1 C126.1 C149.1 C150.1 C186.1 C187.1 C188.1 C189.1 C194.1 ,
        U1.AF10 U1.J1 U1.M3 U1.R3 U1.U2 U5.H2 U5.H10 U6.H2 U6.H10 U26.4 
VTT_3_4 ; C121.1 C197.1 C204.1 C205.1 R67.1 R69.1 R72.1 R74.1 R76.1 R81.1 ,
        R85.1 R86.2 R87.2 R92.1 R94.2 R97.2 R98.2 R101.2 R103.1 R106.1 ,
        R108.1 R109.1 R110.1 R111.1 R116.1 R117.1 R118.1 R119.1 R125.1 ,
        R126.1 R127.1 R128.1 R133.1 R134.1 R135.1 R136.1 R141.1 R142.1 ,
        R143.1 R144.1 R149.1 R150.1 R157.1 R158.1 R160.1 R210.1 R211.1 ,
        R212.1 R213.1 R214.1 R215.1 R216.1 R218.1 R220.1 R221.1 R222.1 ,
        R223.1 R224.1 R225.1 R226.1 R228.1 U25.3 U25.8 
VTT_5_6 ; C195.1 C198.1 C206.1 C207.1 R66.1 R68.1 R71.1 R73.1 R75.1 R78.1 ,
        R82.1 R91.1 R104.1 R107.1 R112.1 R113.1 R114.1 R115.1 R120.1 R121.1 ,
        R122.1 R123.1 R129.1 R130.1 R131.1 R132.1 R137.1 R138.1 R139.1 ,
        R140.1 R145.1 R146.1 R147.1 R148.1 R153.1 R154.1 R161.1 R162.1 ,
        R164.1 R165.2 R166.2 R167.2 R169.2 R170.2 R171.2 R230.1 R231.1 ,
        R232.1 R233.1 R234.1 R235.1 R236.1 R237.1 R239.1 R240.1 R241.1 ,
        R242.1 R243.1 R244.1 R245.1 R246.1 U26.3 U26.8 
WR_N ; U1.V20 U19.41 
$NETS
$A_PROPERTIES
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785233'; 'N16785233'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\5vusb\'; '5VUSB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19791931'; 'N19791931'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19793237'; 'N19793237'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):pwr_detect'; 'PWR_DETECT'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):slcs_n'; 'SLCS_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_ctl5'; 'CY_CTL5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_ctl4'; 'CY_CTL4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_ctl3'; 'CY_CTL3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank8_vcco_sel'; 'BANK8_VCCO_SEL'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19423069'; 'N19423069'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19422816'; 'N19422816'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19422668'; 'N19422668'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19423073'; 'N19423073'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19423126'; 'N19423126'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19423103'; 'N19423103'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19407774'; 'N19407774'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_frame_fdbk'; 'BANK2_FRAME_FDBK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19294394'; 'N19294394'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ifclk_out'; 'IFCLK_OUT'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394530'; 'N19394530'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394463'; 'N19394463'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394296'; 'N19394296'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394229'; 'N19394229'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394086'; 'N19394086'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19394019'; 'N19394019'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19393569'; 'N19393569'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_frame_fdbk'; 'BANK1_FRAME_FDBK'
TOTAL_ETCH_LENGTH '1851 MIL:1881 MIL'; 'SRAM3_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq5'; 'SRAM2_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa21'; 'BANK2_SA21'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq16'; 'SRAM3_DQ16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq1'; 'SRAM2_DQ1'
TOTAL_ETCH_LENGTH '1895 MIL:1925 MIL'; 'SRAM1_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq9'; 'SRAM3_DQ9'
TOTAL_ETCH_LENGTH '1866 MIL:1896 MIL'; 'SRAM3_DQ3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq14'; 'SRAM3_DQ14'
TOTAL_ETCH_LENGTH '3058 MIL:3088 MIL'; 'SRAM2_DQ12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq17'; 'SRAM3_DQ17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq3'; 'SRAM1_DQ3'
TOTAL_ETCH_LENGTH '3005 MIL:3035 MIL'; 'SRAM2_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq16'; 'SRAM4_DQ16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa_0'; 'BANK2_SA_0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq14'; 'SRAM2_DQ14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq17'; 'SRAM4_DQ17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq9'; 'SRAM4_DQ9'
TOTAL_ETCH_LENGTH '3086 MIL:3116 MIL'; 'SRAM4_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa21'; 'BANK1_SA21'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq10'; 'SRAM4_DQ10'
TOTAL_ETCH_LENGTH '1863 MIL:1893 MIL'; 'SRAM1_DQ9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq14'; 'SRAM4_DQ14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq17'; 'SRAM2_DQ17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq5'; 'SRAM1_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq12'; 'SRAM3_DQ12'
TOTAL_ETCH_LENGTH '1796 MIL:1826 MIL'; 'SRAM1_DQ12' 'SRAM3_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq5'; 'SRAM4_DQ5'
TOTAL_ETCH_LENGTH '1871 MIL:1901 MIL'; 'SRAM3_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19046349'; 'N19046349'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ln_n'; 'LN_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vld_n'; 'VLD_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vld_p'; 'VLD_P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ln_p'; 'LN_P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17458107'; 'N17458107'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p5'; 'STOUCH_P5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n4'; 'STOUCH_N4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p0'; 'STOUCH_P0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p4'; 'STOUCH_P4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n1'; 'STOUCH_N1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18969935'; 'N18969935'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p1'; 'STOUCH_P1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p15'; 'STOUCH_P15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n14'; 'STOUCH_N14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n15'; 'STOUCH_N15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n11'; 'STOUCH_N11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):clk_ref_dcm_bypass'; 'CLK_REF_DCM_BYPASS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p2'; 'STOUCH_P2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n9'; 'STOUCH_N9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p14'; 'STOUCH_P14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p13'; 'STOUCH_P13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n0'; 'STOUCH_N0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_nclk'; 'STOUCH_NCLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p12'; 'STOUCH_P12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n5'; 'STOUCH_N5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n7'; 'STOUCH_N7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p9'; 'STOUCH_P9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p11'; 'STOUCH_P11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n2'; 'STOUCH_N2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_pclk'; 'STOUCH_PCLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n13'; 'STOUCH_N13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p7'; 'STOUCH_P7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p8'; 'STOUCH_P8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n3'; 'STOUCH_N3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n10'; 'STOUCH_N10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p10'; 'STOUCH_P10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n12'; 'STOUCH_N12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p6'; 'STOUCH_P6'
TOTAL_ETCH_LENGTH '4125 MIL:4135 MIL'; 'EXP_DATA_P1' 'EXP_DATA_P2' 'EXP_DATA_P3' 'EXP_DATA_P4' 'EXP_DATA_P5' 'EXP_DATA_P6',
           'EXP_DATA_P7' 'EXP_DATA_P8' 'EXP_DATA_P9' 'EXP_DATA_P10' 'EXP_DATA_P11' 'EXP_DATA_P12',
           'EXP_DATA_P13' 'EXP_DATA_P14' 'EXP_DATA_P15' 'EXP_DATA_N0' 'EXP_DATA_N1' 'EXP_DATA_N2',
           'EXP_DATA_N3' 'EXP_DATA_N4' 'EXP_DATA_N5' 'EXP_DATA_N6' 'EXP_DATA_N7' 'EXP_DATA_N8',
           'EXP_DATA_N9' 'EXP_DATA_N10' 'EXP_DATA_N11' 'EXP_DATA_N12' 'EXP_DATA_N13' 'EXP_DATA_N14',
           'EXP_DATA_N15' 'EXP_CLK_P' 'EXP_CLK_N' 'EXP_DATA_P0' 'LN_P' 'VLD_P',
           'VLD_N' 'LN_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):fifoadr0'; 'FIFOADR0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17234750'; 'N17234750'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa1'; 'BANK2_SA1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa1'; 'BANK1_SA1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa19'; 'BANK1_SA19'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa18'; 'BANK1_SA18'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa17'; 'BANK1_SA17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa16'; 'BANK1_SA16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa15'; 'BANK1_SA15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa14'; 'BANK1_SA14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa13'; 'BANK1_SA13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa12'; 'BANK1_SA12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa11'; 'BANK1_SA11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa10'; 'BANK1_SA10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa9'; 'BANK1_SA9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa8'; 'BANK1_SA8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa7'; 'BANK1_SA7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa6'; 'BANK1_SA6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa5'; 'BANK1_SA5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa4'; 'BANK1_SA4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa3'; 'BANK1_SA3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa2'; 'BANK1_SA2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17301402'; 'N17301402'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq8'; 'SRAM2_DQ8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq0'; 'SRAM2_DQ0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq2'; 'SRAM2_DQ2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq11'; 'SRAM2_DQ11'
TOTAL_ETCH_LENGTH '3022 MIL:3052 MIL'; 'SRAM2_DQ13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq4'; 'SRAM2_DQ4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq15'; 'SRAM2_DQ15'
TOTAL_ETCH_LENGTH '3003 MIL:3033 MIL'; 'SRAM2_DQ7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq6'; 'SRAM2_DQ6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq2'; 'SRAM1_DQ2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq0'; 'SRAM1_DQ0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq11'; 'SRAM1_DQ11'
TOTAL_ETCH_LENGTH '1782 MIL:1812 MIL'; 'SRAM1_DQ15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq7'; 'SRAM1_DQ7'
TOTAL_ETCH_LENGTH '1827 MIL:1857 MIL'; 'SRAM1_DQ13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq6'; 'SRAM1_DQ6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq0'; 'SRAM4_DQ0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq7'; 'SRAM4_DQ7'
TOTAL_ETCH_LENGTH '3007 MIL:3037 MIL'; 'SRAM4_DQ15' 'SRAM4_DQ3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq13'; 'SRAM4_DQ13'
TOTAL_ETCH_LENGTH '3002 MIL:3032 MIL'; 'SRAM4_DQ11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq8'; 'SRAM4_DQ8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq6'; 'SRAM4_DQ6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq4'; 'SRAM4_DQ4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq2'; 'SRAM4_DQ2'
TOTAL_ETCH_LENGTH '1816 MIL:1846 MIL'; 'SRAM3_DQ7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq15'; 'SRAM3_DQ15'
TOTAL_ETCH_LENGTH '1784 MIL:1814 MIL'; 'SRAM3_DQ13' 'SRAM1_DQ14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq11'; 'SRAM3_DQ11'
TOTAL_ETCH_LENGTH '1750 MIL:1780 MIL'; 'SRAM3_DQ2' 'SRAM3_DQ4' 'SRAM3_DQ6' 'SRAM3_DQ8' 'SRAM3_DQ0' 'SRAM1_DQ6',
           'SRAM1_DQ8' 'SRAM1_DQ4' 'SRAM1_DQ0' 'SRAM1_DQ2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa20'; 'BANK2_SA20'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa19'; 'BANK2_SA19'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa18'; 'BANK2_SA18'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa17'; 'BANK2_SA17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa16'; 'BANK2_SA16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa15'; 'BANK2_SA15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa14'; 'BANK2_SA14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa13'; 'BANK2_SA13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa12'; 'BANK2_SA12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa11'; 'BANK2_SA11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa10'; 'BANK2_SA10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa9'; 'BANK2_SA9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa8'; 'BANK2_SA8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa7'; 'BANK2_SA7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa6'; 'BANK2_SA6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa5'; 'BANK2_SA5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa4'; 'BANK2_SA4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa3'; 'BANK2_SA3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_sa2'; 'BANK2_SA2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\1v8sram\'; '1V8SRAM'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\3v3dut\'; '3V3DUT'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in30'; 'DATA_IN30'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl5'; 'CTL5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in7'; 'DATA_IN7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in1'; 'DATA_IN1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in35'; 'DATA_IN35'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in20'; 'DATA_IN20'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in21'; 'DATA_IN21'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in15'; 'DATA_IN15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in8'; 'DATA_IN8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in23'; 'DATA_IN23'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl0'; 'CTL0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in10'; 'DATA_IN10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in9_clk'; 'DATA_IN9_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in27_clk'; 'DATA_IN27_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl7'; 'CTL7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in5'; 'DATA_IN5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl3'; 'CTL3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in12'; 'DATA_IN12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in25'; 'DATA_IN25'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in3'; 'DATA_IN3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in34'; 'DATA_IN34'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in13'; 'DATA_IN13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in28'; 'DATA_IN28'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in31'; 'DATA_IN31'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl4'; 'CTL4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in16'; 'DATA_IN16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in29'; 'DATA_IN29'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in32'; 'DATA_IN32'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in17'; 'DATA_IN17'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl6'; 'CTL6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in26'; 'DATA_IN26'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in33'; 'DATA_IN33'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in2'; 'DATA_IN2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in14'; 'DATA_IN14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in22'; 'DATA_IN22'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_clk_fb'; 'DATA_CLK_FB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in19'; 'DATA_IN19'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in6'; 'DATA_IN6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl1'; 'CTL1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in4'; 'DATA_IN4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ctl2'; 'CTL2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in11'; 'DATA_IN11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in24'; 'DATA_IN24'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in63'; 'DATA_IN63'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in62'; 'DATA_IN62'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in61'; 'DATA_IN61'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in60'; 'DATA_IN60'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in59'; 'DATA_IN59'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in58'; 'DATA_IN58'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in57'; 'DATA_IN57'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in56'; 'DATA_IN56'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in55_clk'; 'DATA_IN55_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in54'; 'DATA_IN54'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in53'; 'DATA_IN53'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in52'; 'DATA_IN52'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in51'; 'DATA_IN51'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in48'; 'DATA_IN48'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in47'; 'DATA_IN47'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in46_clk'; 'DATA_IN46_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in45_clk'; 'DATA_IN45_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in44'; 'DATA_IN44'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in43'; 'DATA_IN43'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in42'; 'DATA_IN42'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in41'; 'DATA_IN41'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in38'; 'DATA_IN38'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in37'; 'DATA_IN37'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in36_clk'; 'DATA_IN36_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in18_clk'; 'DATA_IN18_CLK'
SAME_NET_SPACING_CONSTRAINT_SET 'LVDS_L1'; 'DATA_IN0_CLK' 'DATA_IN18_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in0_clk'; 'DATA_IN0_CLK'
TOTAL_ETCH_LENGTH '2580 MIL:2680 MIL'; 'ID0' 'ID1' 'CTL6' 'CTL4' 'CTL7' 'CTL5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\1v2vcc_int\'; '1V2VCC_INT'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sda_from_cy'; 'SDA_FROM_CY'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vin'; 'VIN'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\2v5io\'; '2V5IO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\3v3io\'; '3V3IO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\2v5aux\'; '2V5AUX'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):scl_from_cy'; 'SCL_FROM_CY'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gnd'; 'GND'
ELECTRICAL_CONSTRAINT_SET 'UPREVED_DEFAULT'; 'GND'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):id0'; 'ID0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):id1'; 'ID1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):id2'; 'ID2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):id3'; 'ID3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp3'; 'GP3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp0'; 'GP0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp2'; 'GP2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp1'; 'GP1'
TOTAL_ETCH_LENGTH '2580 MIL:2700 MIL'; 'DATA_IN0_CLK' 'DATA_IN18_CLK' 'DATA_IN24' 'DATA_IN11' 'DATA_IN4' 'DATA_IN6',
           'DATA_IN19' 'DATA_CLK_FB' 'DATA_IN22' 'DATA_IN14' 'DATA_IN2' 'DATA_IN33',
           'DATA_IN26' 'DATA_IN17' 'DATA_IN32' 'DATA_IN29' 'DATA_IN16' 'DATA_IN31',
           'DATA_IN28' 'DATA_IN13' 'DATA_IN34' 'DATA_IN3' 'DATA_IN25' 'DATA_IN12',
           'DATA_IN5' 'DATA_IN27_CLK' 'DATA_IN9_CLK' 'DATA_IN10' 'DATA_IN23' 'DATA_IN8',
           'DATA_IN15' 'DATA_IN21' 'DATA_IN20' 'DATA_IN35' 'DATA_IN1' 'DATA_IN7',
           'DATA_IN30'
TOTAL_ETCH_LENGTH '1800 MIL:1900 MIL'; 'DATA_IN36_CLK' 'DATA_IN37' 'DATA_IN38' 'DATA_IN41' 'DATA_IN42' 'DATA_IN43',
           'DATA_IN44' 'DATA_IN45_CLK' 'DATA_IN46_CLK' 'DATA_IN47' 'DATA_IN48' 'DATA_IN51',
           'DATA_IN52' 'DATA_IN53' 'DATA_IN54' 'DATA_IN55_CLK' 'DATA_IN56' 'DATA_IN57',
           'DATA_IN58' 'DATA_IN59' 'DATA_IN60' 'DATA_IN61' 'DATA_IN62' 'DATA_IN63',
           'DATA_IN64' 'DATA_IN65' 'DATA_IN39_CLK' 'DATA_IN49_CLK' 'DATA_IN66' 'DATA_IN50_CLK',
           'DATA_IN40_CLK' 'DATA_IN67'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq2'; 'SRAM3_DQ2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq4'; 'SRAM3_DQ4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq6'; 'SRAM3_DQ6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq8'; 'SRAM3_DQ8'
TOTAL_ETCH_LENGTH '1786 MIL:1816 MIL'; 'SRAM3_DQ11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq13'; 'SRAM3_DQ13'
TOTAL_ETCH_LENGTH '1787 MIL:1817 MIL'; 'SRAM3_DQ15' 'SRAM1_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq7'; 'SRAM3_DQ7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq0'; 'SRAM3_DQ0'
TOTAL_ETCH_LENGTH '2970 MIL:3000 MIL'; 'SRAM4_DQ2' 'SRAM4_DQ4' 'SRAM4_DQ6' 'SRAM4_DQ8' 'SRAM4_DQ0' 'SRAM2_DQ6',
           'SRAM2_DQ4' 'SRAM2_DQ2' 'SRAM2_DQ0' 'SRAM2_DQ8' 'SRAM4_DQ14' 'SRAM2_DQ14',
           'SRAM2_DQ5' 'SRAM2_DQ3' 'SRAM4_DQ12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq11'; 'SRAM4_DQ11'
TOTAL_ETCH_LENGTH '3052 MIL:3082 MIL'; 'SRAM4_DQ13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq15'; 'SRAM4_DQ15'
TOTAL_ETCH_LENGTH '3073 MIL:3103 MIL'; 'SRAM4_DQ7' 'SRAM2_DQ9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq13'; 'SRAM1_DQ13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq8'; 'SRAM1_DQ8'
TOTAL_ETCH_LENGTH '1812 MIL:1842 MIL'; 'SRAM1_DQ7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq15'; 'SRAM1_DQ15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq4'; 'SRAM1_DQ4'
TOTAL_ETCH_LENGTH '1826 MIL:1856 MIL'; 'SRAM1_DQ11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq7'; 'SRAM2_DQ7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):k1_neg'; 'K1_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa20'; 'BANK1_SA20'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):k1_pls'; 'K1_PLS'
TOTAL_ETCH_LENGTH '3009 MIL:3039 MIL'; 'SRAM2_DQ15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq13'; 'SRAM2_DQ13'
TOTAL_ETCH_LENGTH '3062 MIL:3092 MIL'; 'SRAM2_DQ11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p1'; 'EXP_DATA_P1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\3v3usb\'; '3V3USB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):slrd'; 'SLRD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p2'; 'EXP_DATA_P2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):slwr'; 'SLWR'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):state0'; 'STATE0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p3'; 'EXP_DATA_P3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):state1'; 'STATE1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17307225'; 'N17307225'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p4'; 'EXP_DATA_P4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):state2'; 'STATE2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p5'; 'EXP_DATA_P5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):state3'; 'STATE3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p6'; 'EXP_DATA_P6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p7'; 'EXP_DATA_P7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p8'; 'EXP_DATA_P8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):load_state'; 'LOAD_STATE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p9'; 'EXP_DATA_P9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_req'; 'CY_REQ'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p10'; 'EXP_DATA_P10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17108969'; 'N17108969'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p11'; 'EXP_DATA_P11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p12'; 'EXP_DATA_P12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_valid'; 'CY_VALID'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17109039'; 'N17109039'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p13'; 'EXP_DATA_P13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p14'; 'EXP_DATA_P14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p15'; 'EXP_DATA_P15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n0'; 'EXP_DATA_N0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ifclk'; 'IFCLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n1'; 'EXP_DATA_N1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):flaga'; 'FLAGA'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n2'; 'EXP_DATA_N2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17055879'; 'N17055879'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n3'; 'EXP_DATA_N3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17055981'; 'N17055981'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):programb'; 'PROGRAMB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n4'; 'EXP_DATA_N4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):conf_cclk'; 'CONF_CCLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n5'; 'EXP_DATA_N5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n6'; 'EXP_DATA_N6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n7'; 'EXP_DATA_N7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n8'; 'EXP_DATA_N8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n9'; 'EXP_DATA_N9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n10'; 'EXP_DATA_N10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n11'; 'EXP_DATA_N11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17300278'; 'N17300278'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n12'; 'EXP_DATA_N12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n13'; 'EXP_DATA_N13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n14'; 'EXP_DATA_N14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_n15'; 'EXP_DATA_N15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_bw01'; 'BANK1_BW01'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597500'; 'N178597500'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597860'; 'N178597860'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17300280'; 'N17300280'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597020'; 'N178597020'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597380'; 'N178597380'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597260'; 'N178597260'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n178597620'; 'N178597620'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17121014'; 'N17121014'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sample'; 'SAMPLE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17278098'; 'N17278098'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):overrange'; 'OVERRANGE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17278202'; 'N17278202'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17278222'; 'N17278222'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\1v5io\'; '1V5IO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17278176'; 'N17278176'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17280849'; 'N17280849'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17280725'; 'N17280725'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785881'; 'N16785881'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17280829'; 'N17280829'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17280803'; 'N17280803'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17285435'; 'N17285435'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16721659'; 'N16721659'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17041129'; 'N17041129'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17189786'; 'N17189786'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17258932'; 'N17258932'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_clk_active'; 'LED_CLK_ACTIVE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank8_vcco'; 'BANK8_VCCO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_overrange'; 'LED_OVERRANGE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17258918'; 'N17258918'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\5v\'; '5V'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_sample'; 'LED_SAMPLE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_upload'; 'LED_UPLOAD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):idle'; 'IDLE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16721567'; 'N16721567'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):npower_en'; 'NPOWER_EN'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16722721'; 'N16722721'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):clk_active'; 'CLK_ACTIVE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):upload'; 'UPLOAD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17264627'; 'N17264627'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_idle'; 'LED_IDLE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17193152'; 'N17193152'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17193122'; 'N17193122'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17223723'; 'N17223723'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17223731'; 'N17223731'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17414023'; 'N17414023'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17223745'; 'N17223745'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):conf_initb'; 'CONF_INITB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):dut_vcco_sel'; 'DUT_VCCO_SEL'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\3v3_2v5_io\'; '3V3_2V5_IO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):fpga_reset'; 'FPGA_RESET'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17383990'; 'N17383990'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17383940'; 'N17383940'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17384219'; 'N17384219'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp4'; 'GP4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17321693'; 'N17321693'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp5'; 'GP5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17321679'; 'N17321679'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp6'; 'GP6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp7'; 'GP7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp8'; 'GP8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):gp9'; 'GP9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):v4_tdo'; 'V4_TDO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17309707'; 'N17309707'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17309857'; 'N17309857'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17228694'; 'N17228694'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n182929931'; 'N182929931'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17228718'; 'N17228718'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17122999'; 'N17122999'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17228734'; 'N17228734'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16728417'; 'N16728417'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cs_n'; 'CS_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):rd_n'; 'RD_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):wr_n'; 'WR_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17307246'; 'N17307246'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):v4_tdi'; 'V4_TDI'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):v4_tms'; 'V4_TMS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):conf_done'; 'CONF_DONE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):v4_tck'; 'V4_TCK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17127467'; 'N17127467'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785887'; 'N16785887'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16786312'; 'N16786312'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785324'; 'N16785324'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data3'; 'HP_DATA3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data2'; 'HP_DATA2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data14'; 'HP_DATA14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785129'; 'N16785129'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data12'; 'HP_DATA12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785561'; 'N16785561'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data10'; 'HP_DATA10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data9'; 'HP_DATA9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data11'; 'HP_DATA11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_r_wn'; 'BANK1_R_WN'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_clk'; 'HP_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16786195'; 'N16786195'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data0'; 'HP_DATA0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data6'; 'HP_DATA6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data4'; 'HP_DATA4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data1'; 'HP_DATA1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data7'; 'HP_DATA7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data13'; 'HP_DATA13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17306796'; 'N17306796'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data5'; 'HP_DATA5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data15'; 'HP_DATA15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):hp_data8'; 'HP_DATA8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17135258'; 'N17135258'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17300273'; 'N17300273'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17300265'; 'N17300265'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16727306'; 'N16727306'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16790515'; 'N16790515'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16784821'; 'N16784821'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16785565'; 'N16785565'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n16784934'; 'N16784934'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):usb_power'; 'USB_POWER'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):conf_din'; 'CONF_DIN'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17182422'; 'N17182422'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17182407'; 'N17182407'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17182080'; 'N17182080'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17182215'; 'N17182215'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17231793'; 'N17231793'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17182183'; 'N17182183'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17231837'; 'N17231837'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17231729'; 'N17231729'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sloe'; 'SLOE'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17234762'; 'N17234762'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_clk_p'; 'EXP_CLK_P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17234708'; 'N17234708'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):pktend'; 'PKTEND'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_clk_n'; 'EXP_CLK_N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17234632'; 'N17234632'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):fifoadr1'; 'FIFOADR1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):exp_data_p0'; 'EXP_DATA_P0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):k2_neg'; 'K2_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_r_wn'; 'BANK2_R_WN'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank2_bw01'; 'BANK2_BW01'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):k2_pls'; 'K2_PLS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data7'; 'CY_DATA7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data6'; 'CY_DATA6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data5'; 'CY_DATA5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data4'; 'CY_DATA4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data3'; 'CY_DATA3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data2'; 'CY_DATA2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data1'; 'CY_DATA1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_data0'; 'CY_DATA0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test1p'; 'TEST1P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test3p'; 'TEST3P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test1n'; 'TEST1N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test2n'; 'TEST2N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test4n'; 'TEST4N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test3n'; 'TEST3N'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test4p'; 'TEST4P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):jp_5'; 'JP_5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):jp_1'; 'JP_1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):jp_2'; 'JP_2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):jp_4'; 'JP_4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):jp_3'; 'JP_3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\10pin_gp3\'; '10PIN_GP3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):\10pin_gp2\'; '10PIN_GP2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):spi_sel'; 'SPI_SEL'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):spi_miso'; 'SPI_MISO'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):spi_mosi'; 'SPI_MOSI'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):spi_cs'; 'SPI_CS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):spi_clk'; 'SPI_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr15'; 'CY_ADDR15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr14'; 'CY_ADDR14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr13'; 'CY_ADDR13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr12'; 'CY_ADDR12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr11'; 'CY_ADDR11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr10'; 'CY_ADDR10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr9'; 'CY_ADDR9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr8'; 'CY_ADDR8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr7'; 'CY_ADDR7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr6'; 'CY_ADDR6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr5'; 'CY_ADDR5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd15'; 'CY_FD15'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd14'; 'CY_FD14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr4'; 'CY_ADDR4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr3'; 'CY_ADDR3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd13'; 'CY_FD13'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd12'; 'CY_FD12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr2'; 'CY_ADDR2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr1'; 'CY_ADDR1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd11'; 'CY_FD11'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd10'; 'CY_FD10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_addr0'; 'CY_ADDR0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd9'; 'CY_FD9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd8'; 'CY_FD8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd7'; 'CY_FD7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd6'; 'CY_FD6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd5'; 'CY_FD5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd4'; 'CY_FD4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17462614'; 'N17462614'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd3'; 'CY_FD3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17462381'; 'N17462381'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd2'; 'CY_FD2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17462280'; 'N17462280'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd1'; 'CY_FD1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_fd0'; 'CY_FD0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17853925'; 'N17853925'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17853901'; 'N17853901'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17853999'; 'N17853999'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17854003'; 'N17854003'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17854001'; 'N17854001'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17854005'; 'N17854005'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):test2p'; 'TEST2P'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vref_5_6'; 'VREF_5_6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):flagb'; 'FLAGB'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vtt_3_4'; 'VTT_3_4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vtt_5_6'; 'VTT_5_6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):vref_3_4'; 'VREF_3_4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18048572'; 'N18048572'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18048558'; 'N18048558'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18049603'; 'N18049603'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18049617'; 'N18049617'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18969971'; 'N18969971'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18092594'; 'N18092594'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18092628'; 'N18092628'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n18102458'; 'N18102458'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_id3'; 'CY_ID3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_id2'; 'CY_ID2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_id1'; 'CY_ID1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):cy_id0'; 'CY_ID0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in64'; 'DATA_IN64'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in65'; 'DATA_IN65'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in39_clk'; 'DATA_IN39_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in49_clk'; 'DATA_IN49_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in66'; 'DATA_IN66'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in50_clk'; 'DATA_IN50_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in40_clk'; 'DATA_IN40_CLK'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):data_in67'; 'DATA_IN67'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n17308233'; 'N17308233'
TOTAL_ETCH_LENGTH '630 MIL:650 MIL'; 'STOUCH_P6' 'STOUCH_N12' 'STOUCH_P10' 'STOUCH_N10' 'STOUCH_N3' 'STOUCH_P8',
           'STOUCH_P7' 'STOUCH_N13' 'STOUCH_PCLK' 'STOUCH_N2' 'STOUCH_P11' 'STOUCH_P9',
           'STOUCH_N7' 'STOUCH_N5' 'STOUCH_P12' 'STOUCH_NCLK' 'STOUCH_N0' 'STOUCH_P13',
           'STOUCH_P14' 'STOUCH_N9' 'STOUCH_P2' 'STOUCH_N11' 'STOUCH_N15' 'STOUCH_N14',
           'STOUCH_P15' 'STOUCH_P1' 'STOUCH_N1' 'STOUCH_P4' 'STOUCH_P0' 'STOUCH_N4',
           'STOUCH_P5' 'STOUCH_P3' 'STOUCH_N6' 'STOUCH_N8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq5'; 'SRAM3_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq14'; 'SRAM1_DQ14'
TOTAL_ETCH_LENGTH '3089 MIL:3119 MIL'; 'SRAM4_DQ5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq12'; 'SRAM1_DQ12'
TOTAL_ETCH_LENGTH '1798 MIL:1828 MIL'; 'SRAM3_DQ12' 'SRAM1_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq9'; 'SRAM1_DQ9'
TOTAL_ETCH_LENGTH '3117 MIL:3147 MIL'; 'SRAM4_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq1'; 'SRAM4_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):bank1_sa_0'; 'BANK1_SA_0'
TOTAL_ETCH_LENGTH '3024 MIL:3054 MIL'; 'SRAM4_DQ9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq10'; 'SRAM2_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq9'; 'SRAM2_DQ9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq1'; 'SRAM1_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq16'; 'SRAM2_DQ16'
TOTAL_ETCH_LENGTH '1806 MIL:1836 MIL'; 'SRAM1_DQ3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq12'; 'SRAM2_DQ12'
TOTAL_ETCH_LENGTH '1797 MIL:1827 MIL'; 'SRAM3_DQ14'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq3'; 'SRAM3_DQ3'
TOTAL_ETCH_LENGTH '1830 MIL:1860 MIL'; 'SRAM3_DQ9'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq10'; 'SRAM1_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq3'; 'SRAM4_DQ3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq1'; 'SRAM3_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq17'; 'SRAM1_DQ17'
TOTAL_ETCH_LENGTH '3047 MIL:3077 MIL'; 'SRAM2_DQ1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_dq10'; 'SRAM3_DQ10'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_dq3'; 'SRAM2_DQ3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_dq16'; 'SRAM1_DQ16'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_dq12'; 'SRAM4_DQ12'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):flagc'; 'FLAGC'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_p3'; 'STOUCH_P3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n6'; 'STOUCH_N6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):stouch_n8'; 'STOUCH_N8'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm4'; 'LED_DCM4'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm2'; 'LED_DCM2'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm3'; 'LED_DCM3'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm1'; 'LED_DCM1'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm7'; 'LED_DCM7'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm5'; 'LED_DCM5'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm6'; 'LED_DCM6'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram1_ld'; 'SRAM1_LD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram2_ld'; 'SRAM2_LD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193215990'; 'N193215990'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193216110'; 'N193216110'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193216230'; 'N193216230'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193217070'; 'N193217070'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193216610'; 'N193216610'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c1b_pls'; 'C1B_PLS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c2a_neg'; 'C2A_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c2b_pls'; 'C2B_PLS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c2b_neg'; 'C2B_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c2a_pls'; 'C2A_PLS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c1a_pls'; 'C1A_PLS'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c1a_neg'; 'C1A_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):c1b_neg'; 'C1B_NEG'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram4_ld'; 'SRAM4_LD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):sram3_ld'; 'SRAM3_LD'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):led_dcm0'; 'LED_DCM0'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193238060'; 'N193238060'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193238320'; 'N193238320'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n193240780'; 'N193240780'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19397246'; 'N19397246'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19397543'; 'N19397543'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):ifclk_bidir'; 'IFCLK_BIDIR'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19393654'; 'N19393654'
LOGICAL_PATH '@wv5_rc.schematic1(sch_1):n19373343'; 'N19373343'
TOTAL_ETCH_LENGTH '7400 MIL:7600 MIL'; 'BANK1_FRAME_FDBK' 'BANK2_FRAME_FDBK'
$END
