Rule Violations |
Count |
Minimum Solder Mask Sliver (Gap=3mil) (HasFootprint('MUB10A_L')),(All) |
0 |
Clearance Constraint (Gap=20mil) ((InNet('ADC_CLK'))),(InNet('GND')) |
0 |
Clearance Constraint (Gap=10mil) (All),(All) |
0 |
Minimum Solder Mask Sliver (Gap=3mil) ((HasFootprint('TQFP-64'))),(All) |
0 |
Clearance Constraint (Gap=5mil) ((InComponent('U8'))),(All) |
0 |
Clearance Constraint (Gap=10mil) ((InNet('EXT_ANT') OR InNet('SW_EXT_ANT') OR InNet('L_SW_EXT_ANT') OR InNet('NetC131_1'))),(All) |
0 |
Clearance Constraint (Gap=12mil) ((InNet('PWR_GND') AND IsRegion)),(All) |
0 |
Clearance Constraint (Gap=1mil) ((InComponent('Logo1'))),(All) |
0 |
Minimum Solder Mask Sliver (Gap=4mil) ((InNet('GND') AND InComponent('U1'))),(All) |
0 |
Clearance Constraint (Gap=4mil) (HasFootprint('SDC08B')),(HasFootprint('SDC08B')) |
0 |
Clearance Constraint (Gap=9mil) (InNamedPolygon('Top Layer-ARRAY_NEGATIVE')),(All) |
0 |
Net Antennae (Tolerance=0mil) (All) |
0 |
Silk to Silk (Clearance=5mil) (All),(All) |
0 |
Silkscreen Over Component Pads (Clearance=5mil) (All),(All) |
0 |
Minimum Solder Mask Sliver (Gap=4mil) (All),(All) |
0 |
Hole To Hole Clearance (Gap=10mil) (All),(All) |
0 |
Hole Size Constraint (Min=8mil) (Max=551mil) (All) |
0 |
Minimum Annular Ring (Minimum=9mil) (All) |
0 |
Un-Routed Net Constraint ( (All) ) |
0 |
Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) |
0 |
Width Constraint (Min=6mil) (Max=150mil) (Preferred=10mil) (All) |
0 |
Clearance Constraint (Gap=20mil) (Disabled)((InComponent('ANT1'))),(All) |
0 |
Clearance Constraint (Gap=7mil) (All),(All) |
0 |
Clearance Constraint (Gap=7mil) ((InComponent('U16'))),(All) |
0 |
Clearance Constraint (Gap=7mil) ((InComponent('U11'))),(All) |
0 |
Clearance Constraint (Gap=7mil) ((InComponent('Q6'))),(All) |
0 |
Clearance Constraint (Gap=7mil) ((InComponent('C41'))),(All) |
0 |
Clearance Constraint (Gap=25mil) ((InComponent('T2'))),(All) |
0 |
Width Constraint (Min=10mil) (Max=30mil) (Preferred=10mil) (Disabled)((OnLayer('Top Layer'))) |
0 |
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (Disabled)((InNet('L_SW') AND InComponent('L3'))) |
0 |
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (Disabled)((InNet('L_SW') AND InComponent('L3'))) |
0 |
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=30mil) (Air Gap=10mil) (Entries=4) (Disabled)((InNet('L_SW') AND InComponent('L3'))) |
0 |
Width Constraint (Min=10mil) (Max=50mil) (Preferred=30mil) ((InNet('GND') AND InComponent('U4'))) |
0 |
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=30mil) (Air Gap=10mil) (Entries=2) ((InNet('GND') AND InComponent('U4'))) |
0 |
Clearance Constraint (Gap=25mil) (InNet('R_ADC_CLK')),(InNet('GND')) |
0 |
Clearance Constraint (Gap=25mil) (InNet('ADC_CLK')),(OnLayer('Top Layer')) |
0 |
Width Constraint (Min=30mil) (Max=30mil) (Preferred=30mil) (Disabled)(InNet('EXT_ANT')) |
0 |
Width Constraint (Min=30mil) (Max=30mil) (Preferred=30mil) (Disabled)(InNet('SW_EXT_ANT')) |
0 |
Width Constraint (Min=30mil) (Max=30mil) (Preferred=30mil) (InNet('NetC131_1')) |
0 |
Width Constraint (Min=30mil) (Max=32mil) (Preferred=30mil) (Disabled)(InNet('L_SW_EXT_ANT')) |
0 |
Clearance Constraint (Gap=30mil) ((InNet('TEMP_SENSE_3') AND OnLayer('Bottom Layer'))),(All) |
0 |
Clearance Constraint (Gap=0mil) ((InComponent('T1'))),((InComponent('T3'))) |
0 |
Minimum Solder Mask Sliver (Gap=1mil) ((InComponent('Logo1'))),(All) |
0 |
Clearance Constraint (Gap=20mil) ((InNet('ADC_CLK'))),(InNet('+3.3VDC')) |
0 |
Clearance Constraint (Gap=20mil) ((InNet('ADC_CLK') AND OnLayer('Mid-Layer 1'))),(InNet('GND')) |
0 |
Clearance Constraint (Gap=10mil) ((InNet('ADC_CLK') AND InComponent('R5'))),(All) |
0 |
Clearance Constraint (Gap=20mil) ((OnLayer('Mid-Layer 1') AND InNet('ADC_CLK'))),(All) |
0 |
Room SM73201 - ARC TQFP Test (Bounding Region = (5063mil, 1806mil, 5280mil, 2060mil) (Disabled)(InComponentClass('SM73201 - ARC TQFP Test')) |
0 |
Total |
0 |