************************************************************************
* Clock Distribution Circuits, Texas Instruments		      		   *
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************************************************************************


************************************************************************
*                        Guide for Running the                         *
*                    SSTUB32864 HSPICE Buffer Models                   *
*                                                                      *
*                                                                      *
*              written by Christian Schmoeller, 03/26/2007             *
*                                                                      *
************************************************************************



************************************************************************
*
*   NOTE:
*   The following files must be present in the same directory to 
*	use this SPICE model package:
*      864_how2hspice.txt		        		(Contents list and user guidleines)
*      864_input_buffer_D.hsp 	    			(Data Input Buffer Model)
*      864_input_buffer_D_testbench.hsp 		(Data Input Buffer Model testbench)
*      864_input_buffer_DCS_CSR.hsp 			(CS Input Buffer Model)
*      864_input_buffer_DCS_CSR_testbench.hsp 	(Data Input Buffer Model testbench)
*      864_output_buffer_Q.hsp 	    			(Data Output Buffer Model)
*      864_output_buffer_Q_testbench.hsp 		(Data Output Buffer Model testbench)
*      sstub3286x_lib.l							(Library for nominal material)
*      sstub3286x_lib_weak.l					(Library for weak material)
*      sstub3286x_lib_strong.l					(Library for strong material)
*
*
*   PORTS:
*	The Output Buffer Model has 4 Ports:
*   - IN   :    Buffer Input
*   - OUT  :    Buffer Output
*   - DVDD :    Supply Voltage 
*   - DVSS :    Ground
*
*	All Input Buffer Models have 6 Ports:
*   - D    :    Buffer Input
*   - OUT  :    Buffer Output
*	- RST/NRST:	Reset Port. Attention: Clock input Buffer uses NRST (inverted!), all others RST
*	- VREF :	Reference Voltage	
*   - DVDD :    Supply Voltage 
*   - DVSS :    Ground
*
*   SCALE
*   A Scale is needed for these Model: s=1e-6
*   In the Example testbenches a hierarchical scale 
*   is used. For this you need HSPICE version 2005.03 or above.
*
*   PARASITICS
*   The buffer models do not contain package parasitics. However in the example
*   testbenches you can find a inductivities that are emulating wirebond effects.

 

