D-type latches

Single-bit to 32-bit asynchronous D-type storage registers

Browse by category

Resolve common asynchronous logic and memory issues such as enabling or disabling digital signals or holding signals during reset with our portfolio of more than 180 D-type latches. Included are Schmitt-trigger and 3-state device options available in 1-32 channel configurations.

Select by parametric specification

Voltage

Rating

Packages

Features

Featured D-type latches

Benefits of our D-type latches

checkmark

Schmitt-trigger inputs

Our new HCS family features Schmitt-trigger inputs allowing for superior noise immunity.

checkmark

Diverse package offering

Both leaded and nonleaded packages are available with pin counts ranging from 5 pins to 20 pins. Wettable flanks available on select packages.

checkmark

Wide range of D-type latch functions

Fulfill your design needs with single-bit and asynchronous storage, 1 to 32 channels, and up to 250 MHz clocking

Common applications of D-type latches

Digital signals sometimes need to be enabled or disabled during system operation. This video explores all the options for what to do with the output when a line is disabled, and identifies logic devices that can perform each function.

Technical resources

Application brief

Understanding Schmitt Triggers (Rev. B)

Most CMOS, BiCMOS and TTL devices require fairly fast edges on the high and low transitions on their inputs. If the edges are too slow they can cause excessive current, oscillation and even damage the device.

document-pdfAcrobat

PDF

Application brief

Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A)

The term dual footprint here refers to overlaying two PCB landing pads for two different package configurations. In supply constrained environments, this is a great method to mitigate supply issues for new designs or board spins.

document-pdfAcrobat

PDF

Application note

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

When designing systems that include (CMOS) devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (tri-state).

document-pdfAcrobat

PDF