74ACT11623

ACTIVE

Octal Bus Transceivers With 3-State Outputs

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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 90 ICC @ nom voltage (Max) (mA) 0.04 Propagation delay (Max) (ns) 8.5 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Standard transceiver

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other Standard transceiver

Features

  • Local Bus-Latch Capability
  • Inputs Are TTL-Voltage Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small- Outline Packages and Standard Plastic 300-mil DIPs

    EPIC is a trademark of Texas Instruments Incorporated.

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Description

The 74ACT11623 is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing.

The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (G\BA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of G\BA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for the 74ACT11623.

The 74ACT11623 is characterized for operation from - 40°C to 85°C.

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal Bus Transceiver With 3-State Outputs datasheet (Rev. A) Apr. 01, 1993
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

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