Packaging information
| Package | Pins SSOP (DL) | 56 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 1,000 | LARGE T&R |
Features for the 74ACT16657
- Members of the Texas Instruments WidebusTM Family
- Inputs Are TTL-Voltage Compatible
- Flow-Through Architecture Optimizes PCB Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Description for the 74ACT16657
The 'ACT16657 contain two noninverting octal transceiver sections
with separate parity generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R\ or 2T/R\) input
determines the direction of data flow. When 1T/R\ (or 2T/R\) is high,
data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R\ (or 2T/R\) is low, data flows from the 1B (or 2B)
port to the 1A (or 2A) port (receive mode). When the output-enable
(1
or 2) input is high, both the 1A (or
2A) and 1B (or 2B) ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level,
respectively, on the 1ODD/
(or
2ODD/) input.
1PARITY (or 2PARITY) carries the parity bit value; it is an output
from the parity generator/checker in the transmit mode and an input
to the parity generator/checker in the receive mode.
In the transmit mode, after the 1A (or 2A) bus is polled to
determine the number of high bits, 1PARITY (or 2PARITY) is set to the
logic level that maintains the parity sense selected by the level at
the 1ODD/ (or 2ODD/) input. For example, if 1ODD/ is low (even parity selected) and
there are five high bits on the 1A bus, then 1PARITY is set to the
logic high level so that an even number of the nine total bits (eight
1A-bus bits plus parity bit) are high.
In the receive mode, after the 1B (or 2B) bus is polled to
determine the number of high bits, the 1
(or 2) output logic level indicates
whether or not the data to be received exhibits the correct parity
sense. For example, if 1ODD/ is
high (odd parity selected), 1PARITY is high, and there are three high
bits on the 1B bus, then 1 is
low, indicating a parity error.
The 74ACT16657 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16657 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16657 is characterized for operation from -40°C to 85°C.