Packaging information
| Package | Pins FCCSP (AAV) | 144 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the ADC09QJ800
- ADC Core:
- Resolution: 9 Bit
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
- Performance specifications:
- SNR (–1dBFS, 97MHz): 53.5dBFS
- ENOB (–1dBFS, 97MHz): 8.51Bits
- SFDR (–1dBFS, 97MHz): 64dBFS
- Noise floor (–20dBFS, 97MHz): –140.5dBFS/Hz
- Full-scale input voltage: 800mVPP-DIFF
- Full-power input bandwidth: 6GHz
- JESD204C Serial data interface:
- Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
- Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2 GHz)
- SYSREF Windowing eases synchronization
- Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
- Timestamp input and output for pulsed systems
- Power consumption (800 MSPS):
- Quad Channel: 420mW / channel
- Dual channel: 555mW / channel
- Single channel: 840mW
- Power supplies: 1.1V, 1.9V
Description for the ADC09QJ800
ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.