12-Bit, Dual 500-MSPS or Single 1.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 500, 1000 Resolution (Bits) 12 Number of input channels 2, 1 Interface Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2020 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (Bits) 9.7 SFDR (dB) 74.3 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

BGA (NXA) 292 729 mm² 27 x 27 open-in-new Find other High-speed ADCs (>10MSPS)


  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

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open-in-new Find other High-speed ADCs (>10MSPS)


The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

Data acquisition and analysis software
WAVEVISION5 WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)


  • Provides 4 plot types: Time Domain (Scope), FFT, 2-tone FFT and Histogram
  • Up to 4 data channels per plot
  • Multiple plot windows
  • Continuous data acquisition
  • ACPR Analysis
  • FFT averaging
  • FFT plot exclusion areas
  • Supports hardware and software signal sources
  • Provides ability to read/write hardware's control and (...)

PLUG-INS Download
12-Bit, Dual 800 MSPS or Single 1.6 GSPS A/D Converter Reference Board
ADC12D800RFRB The ADC12Dx00RF is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 12-bit resolution for dual channels at sampling rates of up to 800/500 MSPS (Non-Interleave Mode) or for a single channel up to 1.6/1.0 (...)
  • Configurable to either 1.6 GSPS interleaved or 800 MSPS dual ADC
  • Pin-compatible with ADC12D1x00, ADC10D1000/1500
  • Internally terminated, buffered, differential analog inputs
  • Interleaved timing automatic and manual skew adjust
  • Test patterns at output for system debug
  • Programmable 15-bit gain and 12-bit (...)

Design tools & simulation

SNAM014.ZIP (41 KB) - IBIS Model
SNAC016.ZIP (8114 KB)

Reference designs

Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications
TIDA-00113 This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic performance (...)
document-generic Schematic document-generic User guide
Optimal Clock Sources for GSPS ADCs Reference Design
TIDA-00479 The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
document-generic Schematic document-generic User guide
Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC
TIDA-00071 This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
BGA (NXA) 292 View options

Ordering & quality

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