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High-speed ADCs (≥10 MSPS)

ADC12DJ2700

ACTIVE

12-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling analog-to-digital converter (ADC)

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Data sheet

ADC12DJ2700

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 2700, 5400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2700 Architecture Folding Interpolating SNR (dB) 57.7 ENOB (bit) 9 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 2700, 5400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2700 Architecture Folding Interpolating SNR (dB) 57.7 ENOB (bit) 9 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10 FCCSP (ZEG) 144 100 mm² 10 x 10
  • ADC core:
    • 12-bit resolution
    • Up to 5.4 GSPS in single-channel mode
    • Up to 2.7 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (no signal, VFS = 1.0 VPP-DIFF):
      • Dual-channel mode: –151.6 dBFS/Hz
      • Single-channel mode: –153.8 dBFS/Hz
    • HD2, HD3: –65 dBc up to 3 GHz
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
    • Four independent 32-Bit NCOs per DDC
  • Power consumption: 2.7 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 12-bit resolution
    • Up to 5.4 GSPS in single-channel mode
    • Up to 2.7 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (no signal, VFS = 1.0 VPP-DIFF):
      • Dual-channel mode: –151.6 dBFS/Hz
      • Single-channel mode: –153.8 dBFS/Hz
    • HD2, HD3: –65 dBc up to 3 GHz
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
    • Four independent 32-Bit NCOs per DDC
  • Power consumption: 2.7 W
  • Power supplies: 1.1 V, 1.9 V

The ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to 2700 MSPS and up to 5400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to 2700 MSPS and up to 5400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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Technical documentation

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Type Title Date
* Data sheet ADC12DJ2700 5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 21 Feb 2019
Application notes Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design 30 May 2018
EVM User's guide ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) 09 Jan 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ2700EVM — ADC12DJ2700 12-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling ADC evaluation module

The ADC12DJ2700 evaluation module (EVM) allows for the evaluation of the ADC12DJ2700 device. ADC12DJ2700 is a low-power, 12-bit, dual-channel 2.7-GSPS or single-channel 5.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with (...)

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Simulation model

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Supported products & hardware

Supported products & hardware

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RF-sampling transceivers
AFE7422 — 2-transmit, 2-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 1200-MHz IBW AFE7444 — 4-transmit, 4-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 600-MHz IBW
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Simulation tool

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Reference designs

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Package Pins Download
FCCSP (AAV) 144 View options
FCCSP (ZEG) 144 View options
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