Product details

Sample rate (Max) (MSPS) 3200, 6400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 75 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 3200, 6400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 75 Operating temperature range (C) -40 to 85 Input buffer Yes
FCBGA (AAV) 144 100 mm² 10 x 10
  • ADC core:
    • 12-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (no signal, VFS = 1.0 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.6 dBFS/Hz
    • HD2, HD3: –65 dBc up to 3 GHz
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
    • Four independent 32-Bit NCOs per DDC
  • Power consumption: 3 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 12-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (no signal, VFS = 1.0 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.6 dBFS/Hz
    • HD2, HD3: –65 dBc up to 3 GHz
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
    • Four independent 32-Bit NCOs per DDC
  • Power consumption: 3 W
  • Power supplies: 1.1 V, 1.9 V

The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

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Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ3200EVM — ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module

The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)

In stock
Limit: 9
Evaluation board

TSW14J58EVM — Data capture/pattern generator: data converter EVM with 16 JESD204B/C lanes from 1.6 to 24.5 Gbps

The TSW14J58 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the TI JESD204B/C family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs), and analog front ends (AFEs).

Populated with a Xilinx® (...)

Evaluation board

ABACO-3P-FMC134 — Abaco Systems® direct RF-conversion 4-channel 3.2-GSPS or 2-channel 6.4-GSPS ADC FPGA mezzanine card

The Abaco FMC134 provides four 12-bit 3.2-GSPS or two 12-bit 6.4-GSPS analog-to-digital converters (ADCs). The module highlights the Texas Instruments ADC12DJ3200 two-channel, 12-bit, 3.2-GSPS ADC (two) in a daughtercard with an FPGA mezzanine card (FMC) connector using the JEDEC JESD204B (...)

From: Abaco Systems
Evaluation board

ANNAP-3P-WWDM60 — Annapolis Microsystems 4-channel ADC, 2-channel DAC FPGA mezzanine card up to 10GSPS

This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
From: Annapolis Micro Systems
Evaluation board

PENTEK-3P-71141-XMC — Pentek Model 71141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz ADC, 2-Ch 6.4 GHz DAC Kintex UltraScale - XMC

Accelerate your project by considering a complete off-the-shelf board that utilizes the ADC12DJ3200. The Pentek Jade® Model 71141 is an ideal radar and software radio interface solution that includes the Texas Instrument's ADC12DJ3200 ADC. The solution from Pentek provides a one-channel 6.4GSPS (...)

From: Pentek Inc.
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)

ADC12DJxx00 GUI (Rev. A)

SLAC745A.ZIP (177821 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADC12DJ3200 IBIS Model

SLVMC42.ZIP (36 KB) - IBIS Model
Simulation model

ADC12DJ3200 IBIS-AMI Model

SLVMC55.ZIP (5569 KB) - IBIS-AMI Model
Simulation model

ADC12DJ3200 S-Parameter Model

SLVMD69.ZIP (10 KB) - S-Parameter Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Reference designs

TIDA-010122 — Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems

This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA), (...)
Reference designs

TIDA-01028 — 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design (...)
Reference designs

TIDA-01027 — Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems

This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content. (...)
Reference designs

TIDA-01442 — Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design

The TIDA-01442 reference design utilizes the ADC12DJ3200 evaluation module (EVM) to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C-, and part of X-band. The wide analog input bandwidth and high sampling rate (6.4 GSPS) of the analog-to-digital (...)
Reference designs

TIDA-01021 — Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
Reference designs

TIDA-01024 — High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
Reference designs

TIDA-01023 — High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
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