Product details

Sample rate (Max) (MSPS) 370 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.7 Power consumption (Typ) (mW) 1607 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 88 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 370 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.7 Power consumption (Typ) (mW) 1607 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 88 Operating temperature range (C) -40 to 85 Input buffer Yes
WQFN (RME) 56 64 mm² 8 x 8
  • Resolution: 16-Bit
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • Performance:
    • Input: 150 MHz, –3 dBFS
      • SNR: 69.6 dBFS
      • Noise Spectral Density: –152.3 dBFS/Hz
      • SFDR: 88 dBFS
      • Non-HD2 and Non-HD3 SPUR: –90 dBFS
  • Power Dissipation: 800 mW/channel
  • Buffered Analog Inputs
  • On-Chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider With Phase Synchronization
    (Divide-by- 1, 2, 4, or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-Lanes/Channel
  • Fast Over-Range Signals
  • 4-Wire, 1.2-V, 1.8-V, 2.5-V, or 3-V Compatible Serial
    Peripheral Interface (SPI)
  • 56-Pin WQFN Package, (8 × 8 mm, 0.5-mm Pin-Pitch)
  • Resolution: 16-Bit
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • Performance:
    • Input: 150 MHz, –3 dBFS
      • SNR: 69.6 dBFS
      • Noise Spectral Density: –152.3 dBFS/Hz
      • SFDR: 88 dBFS
      • Non-HD2 and Non-HD3 SPUR: –90 dBFS
  • Power Dissipation: 800 mW/channel
  • Buffered Analog Inputs
  • On-Chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider With Phase Synchronization
    (Divide-by- 1, 2, 4, or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-Lanes/Channel
  • Fast Over-Range Signals
  • 4-Wire, 1.2-V, 1.8-V, 2.5-V, or 3-V Compatible Serial
    Peripheral Interface (SPI)
  • 56-Pin WQFN Package, (8 × 8 mm, 0.5-mm Pin-Pitch)

The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

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Technical documentation

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Type Title Date
* Data sheet ADC16DX370 Dual 16-Bit 370 MSPS ADC With 7.4 Gb/s JESD204B Outputs datasheet (Rev. C) 20 Aug 2014
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mar 2015
User guide ADC16DX370EVM User's Guide (Rev. A) 17 Dec 2014
Application note Equalization Optimization of the ADC16DX370 JESD204B Serial Link 09 Sep 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC16DX370EVM — ADC16DX370 Evaluation Module

The ADC16DX370EVM is an evaluation module used for evaluation of the ADC16DX370.  The ADC16DX370 is a low power, 16-bit, 370-MSPS analog to digital converter (ADC) with a buffered analog input, and outputs featuring a JESD204B interface operating at up to 7.4Gb/s. The EVM has (...)

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Evaluation board

TSW16DX370EVM — TSW16DX370EVM Evaluation Module

The TSW16DX370EVM is a reference design board used to evaluate the high performance receiver IF super-heterodyne subsystem solution including the following products from Texas Instruments:

  • TRF37B32 dual down-converting mixer with integrated IF amplifier
  • LMH6521 dual digitally controlled variable gain (...)
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Limit: 3
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

ADC16DX370 IBIS Model (Rev. A)

SNVM586A.ZIP (38 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
参考设计

TIDA-00360 — 700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design

The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver (...)
参考设计

TIDA-00353 — Equalization Optimization of a JESD204B Serial Link Reference Design

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
参考设计

TIDA-00153 — JESD204B Link Latency Design Using a High Speed ADC

JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface (...)
Package Pins Download
WQFN (RME) 56 View options

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