Product details

Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 454 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.8 SFDR (dB) 96 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 454 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.8 SFDR (dB) 96 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultralow Power Consumption:
    • 227 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multichip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
    (ADC32J2X)
  • Package: VQFN-48 (7 mm × 7 mm)
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultralow Power Consumption:
    • 227 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multichip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
    (ADC32J2X)
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

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Technical documentation

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Type Title Date
* Data sheet ADC32J4x Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters with JESD204B Interface datasheet (Rev. A) 26 May 2015
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
User guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Design guide Optical Front-End System Design Guide 26 Oct 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC32J45EVM — ADC32J45 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module

The ADC32J45 EVM demonstrates the performance of a low power dual 160Msps 14 bit ADC. It includes the ADC32J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)

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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

ADC34J45 IBIS Model

SBAM204.ZIP (79 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00294 — High Perf Single Ended to Diff Active Interface for High Speed ADC Developed by Dallas Logic Corp

This reference design uses the ADC34J22 12b 50Msps JESD204B data converter and the THS4541 fully differential amplifer to demonstrate how to design a high performance active interface for high speed ADCs.  This type of circuit can be used in sensor front end, motor control, and test and (...)
From: Dallas Logic Corporation
Package Pins Download
VQFN (RGZ) 48 View options

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