Firmware
ADC32RF44
Dual-Channel, 14-Bit, 2.6-GSPS RF-Sampling Analog-to-Digital Converter (ADC)
Data sheet
ADC32RF44
- 14-Bit, Dual-Channel, 2.6-GSPS ADC
- Noise Floor: –154.2 dBFS/Hz
- RF Input Supports Up to 4.0 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance (fIN = 900 MHz, –2 dBFS):
- SNR: 61.2 dBFS
- SFDR: 65-dBc HD2, HD3
- SFDR: 79-dBc Worst Spur
- Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
- SNR: 58.3 dBFS
- SFDR: 69-dBc HD2, HD3
- SFDR: 74-dBc Worst Spur
- On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel at 12.5 Gbps
- Power Dissipation: 2.95 W/Ch at 2.6 GSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
The ADC32RF44 device is a 14-bit, 2.6-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF44 delivers a noise spectral density of –154.2 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF44 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
Technical documentation
No results found. Please clear your search and try again.
View all 4 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter datasheet (Rev. A) | PDF | HTML | 23 Mar 2017 |
| EVM User's guide | ADC32RFxxEVM User's Guide (Rev. E) | 31 Jan 2020 | ||
| Application note | Spurs Analysis in the RF Sampling ADC | 09 Feb 2018 | ||
| Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 05 Sep 2017 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
ADC32RF44EVM — ADC32RF44 Dual-Channel, 14-Bit, 2.6GSPS, RF-Sampling ADC Evaluation Module
The ADC32RF44 evaluation module (EVM) demonstrates the performance of a dual 2.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF44 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)
User guide: PDF
Firmware
SBAC187 — KCU105 + ADC32RF44 Design Firmware
Supported products & hardware
Products
High-speed ADCs (≥10 MSPS)
Hardware development
Evaluation board
Firmware
TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)
SBAC148 — ADC32RFxxEVM SPI GUI Installer
Supported products & hardware
Products
Receivers
High-speed ADCs (≥10 MSPS)
Hardware development
Evaluation board
Calculation tool
FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
Supported products & hardware
Products
Receivers
High-speed ADCs (≥10 MSPS)
RF-sampling transceivers
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| Package | Pins | Download |
|---|---|---|
| VQFNP (RMP) | 72 | View options |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Information included:
- Fab location
- Assembly location
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.