Product details

Sample rate (Max) (MSPS) 65 Resolution (Bits) 16 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Performance, Low Power Rating Catalog Input range (Vp-p) 3.2 Power consumption (Typ) (mW) 142 Architecture SAR SNR (dB) 82 ENOB (Bits) 13.3 SFDR (dB) 90 Operating temperature range (C) -40 to 105 Input buffer No
Sample rate (Max) (MSPS) 65 Resolution (Bits) 16 Number of input channels 2 Interface type CMOS Analog input BW (MHz) 900 Features High Performance, Low Power Rating Catalog Input range (Vp-p) 3.2 Power consumption (Typ) (mW) 142 Architecture SAR SNR (dB) 82 ENOB (Bits) 13.3 SFDR (dB) 90 Operating temperature range (C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • Dual channel
  • 16-bit 65 MSPS ADC (max output rate = 31 Msps)
  • Noise floor: –159 dBFS/Hz
  • Ultra-low power: 71 mW/ch at 65 MSPS
  • 16-Bit, no missing codes
  • INL: ±2 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3 dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital down converter
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial CMOS interface
  • Single 1.8-V supply
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 81.9 dBFS
    • SFDR: 88 dBc HD2, HD3
    • SFDR: 102 dBFS worst spur
  • Dual channel
  • 16-bit 65 MSPS ADC (max output rate = 31 Msps)
  • Noise floor: –159 dBFS/Hz
  • Ultra-low power: 71 mW/ch at 65 MSPS
  • 16-Bit, no missing codes
  • INL: ±2 LSB; DNL: ±0.2 LSB
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3 dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital down converter
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial CMOS interface
  • Single 1.8-V supply
  • Small footprint: 40-WQFN (5 mm × 5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 81.9 dBFS
    • SFDR: 88 dBc HD2, HD3
    • SFDR: 102 dBFS worst spur

The ADC3660 device is a low-noise, ultra-low power, 16-bit, 65-MSPS dual-channel, high-speed analog-to-digital converter (ADCs). Designed for low power consumption, the device delivers a noise spectral density of –159 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC3660 offers excellent dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. The ADC consumes only 71 mW/ch at 65 MSPS, and power consumption scales very well with lower sampling rates. In bypass mode (up to 31 MSPS) the output data is available after 1 or 2 clock cycles.

The ADC3660 uses a serial CMOS (SCMOS) interface to output the data which minimizes the number of digital interconnects. The device supports a two-lane, a one-lane and a half lane option. The serialized CMOS interface supports output rates to 250 Mbps which translates to ~ 15 MSPS (2-wire) to ~ 3.75 MSPS (0.5-wire) output rates after complex decimation. Hence the ADC3660 can be operated in ’oversampling + decimating’ mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The device comes in a 40-pin WQFN package (5 mm × 5 mm) and supports the extended industrial temperature range of –40 to +105⁰C.

The ADC3660 device is a low-noise, ultra-low power, 16-bit, 65-MSPS dual-channel, high-speed analog-to-digital converter (ADCs). Designed for low power consumption, the device delivers a noise spectral density of –159 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC3660 offers excellent dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. The ADC consumes only 71 mW/ch at 65 MSPS, and power consumption scales very well with lower sampling rates. In bypass mode (up to 31 MSPS) the output data is available after 1 or 2 clock cycles.

The ADC3660 uses a serial CMOS (SCMOS) interface to output the data which minimizes the number of digital interconnects. The device supports a two-lane, a one-lane and a half lane option. The serialized CMOS interface supports output rates to 250 Mbps which translates to ~ 15 MSPS (2-wire) to ~ 3.75 MSPS (0.5-wire) output rates after complex decimation. Hence the ADC3660 can be operated in ’oversampling + decimating’ mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The device comes in a 40-pin WQFN package (5 mm × 5 mm) and supports the extended industrial temperature range of –40 to +105⁰C.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 9
Type Title Date
* Data sheet ADC3660 16-Bit, 0.5 to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet (Rev. A) 26 Oct 2020
Application note High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs 09 Dec 2020
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization 08 Dec 2020
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
User guide ADC3660 Evaluation Module User's Guide 27 Jul 2020
Analog design journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC3660EVM — ADC3660 dual, 16-bit, 0.5-MSPS to 65-MSPS, low-noise, ultra-low-power ADC evaluation module

The ADC3660 evaluation module (EVM) demonstrates the performance of the ADC3660, which is an ultra-low-power, high-linearity, analog-to-digital converter (ADC). Onboard voltage regulation and flexible analog input options allow easy evaluation for many different applications.

For a complete (...)

In stock
Limit: 3
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

Example Electrosurgery Reference Design

SLOM512.ZIP (58 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

ADC35XXEVM CMOS Interposer Design Files

SBAR017.ZIP (7671 KB)
Package Pins Download
WQFN (RSB) 40 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos