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ADC3669

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16-bit, two-channel, 500-MSPS ADC with LVDS interface and up to 16384x decimation

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Data sheet

ADC3669

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (bps) 16 Number of input channels 2 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 75.2 ENOB (bit) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (bps) 16 Number of input channels 2 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 75.2 ENOB (bit) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² 9 x 9
  • 16-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR/Serial LVDS interface
    • 16-bit Parallel DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation
  • Power consumption: 300mW/channel (500MSPS)
  • 16-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR/Serial LVDS interface
    • 16-bit Parallel DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation
  • Power consumption: 300mW/channel (500MSPS)

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
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* Data sheet ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet PDF | HTML 24 Sep 2024
Analog Design Journal The art of passive matching a high-speed ADC analog-input front end PDF | HTML 23 Sep 2024
Certificate ADC3669EVM EU Declaration of Conformity (DoC) (Rev. A) 11 Sep 2024

Design & development

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Evaluation board

ADC3669EVM — ADC3669 evaluation module

The ADC3669EVM is designed to evaluate the ADC3669 family of high-speed analog-to-digital converters (ADCs). The ADC3669EVM is populated with an ADC3669, a 16-bit dual-channel ADC with an LVDS interface that can operate at sample rates up to 500MSPS. The ADC3669EVM allows for evaluation of all (...)
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Simulation model

ADC3669 IBIS Model

SBAM516.ZIP (39 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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