Product details

Resolution (Bits) 32 Number of input channels 2 Sample rate (Max) (kSPS) 4 Interface type SPI Architecture Delta-Sigma Input type Differential Multi-channel configuration Multiplexed Rating Catalog Input range (Max) (V) 2.5 Input range (Min) (V) -2.5 Features GPIO, PGA Operating temperature range (C) -40 to 85 Power consumption (Typ) (mW) 8 Analog voltage AVDD (Min) (V) 3 SNR (dB) 134 Analog voltage AVDD (Max) (V) 5.5 Digital supply (Min) (V) 1.65 Digital supply (Max) (V) 3.6
Resolution (Bits) 32 Number of input channels 2 Sample rate (Max) (kSPS) 4 Interface type SPI Architecture Delta-Sigma Input type Differential Multi-channel configuration Multiplexed Rating Catalog Input range (Max) (V) 2.5 Input range (Min) (V) -2.5 Features GPIO, PGA Operating temperature range (C) -40 to 85 Power consumption (Typ) (mW) 8 Analog voltage AVDD (Min) (V) 3 SNR (dB) 134 Analog voltage AVDD (Max) (V) 5.5 Digital supply (Min) (V) 1.65 Digital supply (Max) (V) 3.6
VQFN (RHB) 32
  • Power-scalable modes (DR at 500 SPS, gain = 1):
    • High-power mode: 134-dB DR, 11.5 mW
    • Mid-power mode: 134-dB DR, 8.5 mW
    • Low-power mode: 131-dB DR, 6.5 mW
  • THD: –120 dB
  • CMRR: 125 dB
  • Data rate: 125 SPS to 4000 SPS
  • PGA gain: 1 to 64
  • Power-saving buffer mode
  • Sample rate converter
  • Linear- and minimum-phase digital filter
  • Programmable high-pass filter
  • Test input channel
  • Offset and gain calibration
  • General-purpose I/Os
  • Analog power supply: 3.3 V or 5 V
  • Single or dual power-supply operation
  • Reference option: 5 V, 4.096 V, or 2.5 V
  • Power-scalable modes (DR at 500 SPS, gain = 1):
    • High-power mode: 134-dB DR, 11.5 mW
    • Mid-power mode: 134-dB DR, 8.5 mW
    • Low-power mode: 131-dB DR, 6.5 mW
  • THD: –120 dB
  • CMRR: 125 dB
  • Data rate: 125 SPS to 4000 SPS
  • PGA gain: 1 to 64
  • Power-saving buffer mode
  • Sample rate converter
  • Linear- and minimum-phase digital filter
  • Programmable high-pass filter
  • Test input channel
  • Offset and gain calibration
  • General-purpose I/Os
  • Analog power supply: 3.3 V or 5 V
  • Single or dual power-supply operation
  • Reference option: 5 V, 4.096 V, or 2.5 V

The ADS1285 is a high-resolution, low-power consumption, analog-to-digital converter (ADC), with a programmable gain amplifier (PGA) and a finite impulse response (FIR) filter. The ADC is suitable for the demanding needs of seismic equipment requiring precision digitization with long battery run time.

The ADC features a low-noise PGA (6 nV/√Hz) suitable for direct connection to geophones and transformer-coupled hydrophones without the need of external amplifiers.

Power-scalable modes trade-off dynamic range against power consumption. Optional buffer operation bypasses the PGA to further reduce power consumption.

The ADC incorporates a high-resolution, low-drift, delta-sigma (ΔΣ) modulator and a FIR digital filter with programmable phase response. The high-pass filter (HPF) removes dc and low-frequency content from the signal. The sample rate converter (SRC) corrects the effect of clock frequency error to within 7-ppb resolution.

The ADC is available in a compact 5-mm × 5-mm VQFN package and is fully specified over the –40°C to +85°C temperature range.

The ADS1285 is a high-resolution, low-power consumption, analog-to-digital converter (ADC), with a programmable gain amplifier (PGA) and a finite impulse response (FIR) filter. The ADC is suitable for the demanding needs of seismic equipment requiring precision digitization with long battery run time.

The ADC features a low-noise PGA (6 nV/√Hz) suitable for direct connection to geophones and transformer-coupled hydrophones without the need of external amplifiers.

Power-scalable modes trade-off dynamic range against power consumption. Optional buffer operation bypasses the PGA to further reduce power consumption.

The ADC incorporates a high-resolution, low-drift, delta-sigma (ΔΣ) modulator and a FIR digital filter with programmable phase response. The high-pass filter (HPF) removes dc and low-frequency content from the signal. The sample rate converter (SRC) corrects the effect of clock frequency error to within 7-ppb resolution.

The ADC is available in a compact 5-mm × 5-mm VQFN package and is fully specified over the –40°C to +85°C temperature range.

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* Data sheet ADS1285 High-Resolution, Delta-Sigma ADC for Seismic Applications datasheet 04 May 2022
User guide ADS1285EVM-PDK User's Guide 12 Apr 2022

Design & development

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Evaluation board

ADS1285EVM-PDK — ADS1285 performance demonstration kit for 32-bit, high-resolution, two-channel delta-sigma ADC

The ADS1285 evaluation module (EVM) performance demonstration kit (PDK) is a platform that combines the ADS1285EVM-PDK and a precision host interface (PHI) controller board. The PHI controller board allows the ADS1285EVM to connect to a computer via a USB port, which interfaces with software that (...)

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ADC-INPUT-CALC — Analog-to-digital converter (ADC) input driver design tool supporting multiple input types

ADC-INPUT-CALC is an online tool that provides support for designing the input buffer to an analog-to-digital converter (ADC). It offers 24 different op-amp based buffer circuits that can be used to drive an ADC input. The available topologies cover differential, single-ended and (...)
Calculation tool

ANALOG-ENGINEER-CALC — Analog engineer's calculator

The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
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VQFN (RHB) 32 View options

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