Product details

Sample rate (Max) (MSPS) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 350 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.2 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 350 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.2 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • ADS41B49: 14-Bit, 250 MSPS
    ADS41B29: 12-Bit, 250 MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance: 2 pF
    • 200-MHz Input Resistance: 3 kΩ
  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 1.8-V Analog Power: 180 mW
    • 3.3-V Buffer Power: 96 mW
    • I/O Power: 135 mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 82.5 dBc at 170 MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: VQFN-48 (7 mm × 7 mm)
  • ADS41B49: 14-Bit, 250 MSPS
    ADS41B29: 12-Bit, 250 MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance: 2 pF
    • 200-MHz Input Resistance: 3 kΩ
  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 1.8-V Analog Power: 180 mW
    • 3.3-V Buffer Power: 96 mW
    • I/O Power: 135 mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 82.5 dBc at 170 MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: VQFN-48 (7 mm × 7 mm)

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

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Technical documentation

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Type Title Date
* Data sheet ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers datasheet (Rev. F) 11 Feb 2016
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
User guide ADS41xx/58B18EVM User's Guide.. (Rev. C) 15 May 2012
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
Application note Power Supply Design for the ADS41xx (Rev. A) 29 Dec 2011
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS4149EVM — ADS4149 14-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS4149EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4149 device, an extremely low power 14-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible (...)

In stock
Limit: 3
Evaluation board

ADS41B29EVM — ADS41B29 12-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS41B29EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B29 device, an extremely low power 12-bit 250 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)

In stock
Limit: 1
Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample (...)

Out of stock on TI.com
Evaluation board

TSW3085EVM — Wideband Transmit Signal Chain Evaluation Board and Reference Design

The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

In stock
Limit: 3
GUI for evaluation module (EVM)

ADS41xx SPI GUI rev1.6 (Rev. B)

SLAC384B.ZIP (82933 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Support software

TIGAR Support Files

SBAC120.ZIP (262219 KB)
Simulation model

ADS414x, ADS412x, ADS58B1x, IBIS MODEL

SBAM091.ZIP (318 KB) - IBIS Model
Simulation model

ADS414x, ADS412x, ADS58B1x, IBIS MODEL (Rev. A)

SBAM091A.ZIP (318 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

JITTER-SNR-CALC — Jitter and SNR Calculator for ADCs

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
Bill of materials (BOM)

ADS41xx EVM BOM, Schematic, and PCB

SLAR048.ZIP (2222 KB)
Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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