Product details

Number of input channels 4 Resolution (Bits) 14 Sample rate (Max) (MSPS) 500 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 900 SFDR (Typ) (dB) 85 SNR (Typ) (dB) 65.8 Power consumption (Typ) (mW) 3270 Logic voltage DV/DD (Max) (V) 1.9 Logic voltage DV/DD (Min) (V) 1.7 Analog voltage AVDD (Max) (V) 2 Analog voltage AVDD (Min) (V) 1.8 Operating temperature range (C) -40 to 85
Number of input channels 4 Resolution (Bits) 14 Sample rate (Max) (MSPS) 500 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 900 SFDR (Typ) (dB) 85 SNR (Typ) (dB) 65.8 Power consumption (Typ) (mW) 3270 Logic voltage DV/DD (Max) (V) 1.9 Logic voltage DV/DD (Min) (V) 1.7 Analog voltage AVDD (Max) (V) 2 Analog voltage AVDD (Min) (V) 1.8 Operating temperature range (C) -40 to 85
VQFN (RGC) 64 81 mm² 9 x 9
  • 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
  • Power Amplifier Linearization (Feedback) Modes
    • 14-Bits Every Other Sample at 250MSPS
    • Programmable Resolution vs Duty Cycle
      • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
      • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
      • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
  • Traffic Receiver Modes
    • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
    • 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
    • 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
  • Flexible Input Clock Buffer With Divide by 1/2/4
  • JESD204B Digital Interface up to 5.0Gbps
    • 1 or 2 Lanes per Channel, With Subclass 1
  • 64-Pin VQFN Package (9 × 9 mm)
  • 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
  • Power Amplifier Linearization (Feedback) Modes
    • 14-Bits Every Other Sample at 250MSPS
    • Programmable Resolution vs Duty Cycle
      • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
      • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
      • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
  • Traffic Receiver Modes
    • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
    • 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
    • 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
  • Flexible Input Clock Buffer With Divide by 1/2/4
  • JESD204B Digital Interface up to 5.0Gbps
    • 1 or 2 Lanes per Channel, With Subclass 1
  • 64-Pin VQFN Package (9 × 9 mm)

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.

Key Specifications:

  • Power Dissipation: 875 mW/ch
  • Input Bandwidth (3dB): 900 MHz
  • Aperture Jitter: 98 fs rms
  • Channel Isolation: 85 dB
  • Performance at in = 170 MHz at 1.25 Vpp,
    –1 dBFS
    • SNR: 65.8 dBFS
    • SFDR: 85 dBc HD2,3 95 dBFS non HD2,3

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.

Key Specifications:

  • Power Dissipation: 875 mW/ch
  • Input Bandwidth (3dB): 900 MHz
  • Aperture Jitter: 98 fs rms
  • Channel Isolation: 85 dB
  • Performance at in = 170 MHz at 1.25 Vpp,
    –1 dBFS
    • SNR: 65.8 dBFS
    • SFDR: 85 dBc HD2,3 95 dBFS non HD2,3

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Technical documentation

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Type Title Date
* Data sheet ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC datasheet 24 Nov 2014
Technical article Why should you care about the noise immunity of MLVDS drivers and receivers? 26 Jul 2017
Technical article How to minimize filter loss when you drive an ADC 20 Oct 2016
Technical article RF sampling: analog-to-digital converter linearity sets sensitivity 29 Sep 2016
Technical article RF sampling: linearity performance is not so straightforward 30 Aug 2016
EVM User's guide ADS58J89 EVM User's Guide (Rev. A) 12 Jan 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS58J89EVM — ADS58J89 Evaluation Module

The ADS58J89 EVM demonstrates the performance of a quad 500Msps Receiver and Feedback IC with the JESD204B interface. It includes the ADS58J89 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for each channel of the ADC (...)

GUI for evaluation module (EVM)

ADS58J89 EVM SPI GUI Installer v1.1 (Rev. A)

SLAC506A.ZIP (184962 KB)
lock = Requires export approval (1 minute)
Simulation model

ADS54J54 and ADS58J89 IBIS Model

SBAM247.ZIP (31 KB) - IBIS Model
Package Pins Download
VQFN (RGC) 64 View options

Ordering & quality

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