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Product details

Parameters

Sample rate (Max) (MSPS) 20 Resolution (Bits) 10 Number of input channels 1 Interface Parallel CMOS Analog input BW (MHz) 100 Features Low Power Rating Catalog Input range (Vp-p) 1, 2 Power consumption (Typ) (mW) 54 Architecture Pipeline SNR (dB) 49 ENOB (Bits) 7.9 SFDR (dB) 53 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

SSOP (DB) 28 54 mm² 5.3 x 10.2 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • +2.7V TO +3.7V SUPPLY OPERATION
  • INTERNAL REFERENCE
  • LOW POWER: 52mW at +3V
  • SINGLE-ENDED INPUT RANGE: 1V to 2V
  • WIDEBAND TRACK/HOLD: 350MHz
  • SSOP-28 PACKAGE
  • APPLICATIONS
    • PORTABLE INSTRUMENTATION
    • IF AND BASEBAND COMMUNICATIONS
    • CABLE MODEMS
    • SET-TOP BOXES
    • PORTABLE TEST EQUIPMENT
    • COMPUTER SCANNERS
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS900 is a high-speed pipelined Analog-to-Digital Converter (ADC). This complete converter includes a high bandwidth track-and-hold, a 10-bit quantizer, and an internal reference.

The ADS900 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications.

This high-performance ADC is specified for performance at a 20MHz sampling rate. The ADS900 is available in an SSOP-28 package.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet ADS900: SpeedPlus? 10-Bit, 20MHz, +3V Supply Analog-To-Digital Converter datasheet (Rev. A) Feb. 23, 2001
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

CALCULATION TOOLS Download
Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

CAD/CAE symbols

Package Pins Download
SSOP (DB) 28 View options

Ordering & quality

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