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AM69A

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32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX

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AM69A

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Product details

Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BSX-64-4, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 2MB shared L2 cache per quad-core Cortex®-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core
  • Up to Four Deep Learning Accelerators:
    • Each with up to 8 Trillion Operations Per Second (TOPS)
    • Total of 32 Trillion Operations Per Second (32 TOPS)
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
  • GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s

  • Multimedia:

    • Display subsystem supports:
      • Up to 4 displays
      • Up to two DSI 4L TX (up to 2.5K)
      • One eDP 4L
      • One DPI 24-bit RGB parallel interface
      • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
      • Safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • IMG BSX-64-4, up to 800 MHz
      • 50 GFLOPS, 4 GTexels/s
      • >500 MTexels/s, >8 GFLOPs
      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
      • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
      • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
    • Two Video Encoder/Decoder Modules
      • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
      • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
      • Support for up to 4K UHD resolution (3840 × 2160) per module
      • Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 external ports
    • Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.
  • Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD

    Ethernet

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The AM69A scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69A provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69A class of processors.

The AM69A scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69A provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total) of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four “MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS per core] within the lowest power envelope in the industry, even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the AM69A class of processors.
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Technical documentation

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Type Title Date
* Data sheet AM69Ax Processors, Silicon Revision 1.0 datasheet PDF | HTML 28 Feb 2023
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 PDF | HTML 15 Feb 2022
Application note Building an Edge AI Application for Automated Retail Scanner on AM6xA MPUs PDF | HTML 17 May 2023
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. E) PDF | HTML 15 May 2023
Application note Jacinto7 AM6x/DRA8x/TDA4x Schematic Checklist (Rev. A) PDF | HTML 12 May 2023
Application note AM6xA ISP Tuning Guide PDF | HTML 02 Mar 2023
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 01 Mar 2023
User guide J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. B) 09 Nov 2022
Technical article How to simplify your embedded edge AI application development 28 Jan 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SK-AM69 — Starter kit for Sitara™ processors

The SK-AM69 Starter Kit/Evaluation Module (EVM) is based on the AM69x AI vision processor which includes an image signal processor (ISP) supporting up to 1440MP/s, 32 tera-operations-per-second (TOPS) AI accelerator, eight 64-bit Arm®-Cortex® A72 microprocessor, and H.264/H.265 video (...)

User guide: PDF | HTML
Not available on TI.com
Software development kit (SDK)

PROCESSOR-SDK-LINUX-AM69A — Processor SDK Linux for AM69A

The AM69A processor software development kit (SDK) is a unified software platform includes access to benchmarks, demonstrations, drivers and more for easy setup and out-of-box development of Linux(R)-based designs. 
All releases of this SDK allow developers to seamlessly reuse and develop software (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX
Hardware development
Evaluation board
SK-AM69 — Starter kit for Sitara™ processors
Download options
IDE, configuration, compiler or debugger

C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4VM — Dual Arm® Cortex®-A72 SoC and C7x DSP with deep-learning, vision and multimedia accelerators TDA4VM-Q1 — Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning AM62A3 — 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A7 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation
Download options
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Products
Automotive mmWave radar sensors
AWR1243 — 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 — 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 — Automotive 2nd-generation, 76-GHz to 81-GHz, high-performance SoC for corner and long-range radar AWR6443 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU
Industrial mmWave radar sensors
IWR1443 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 — Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
Launch Download options
IDE, configuration, compiler or debugger

EDGE-AI-STUDIO — Edge AI studio

Edge AI Studio is a collection of tools aimed to accelerate the development of edge AI application on TI embedded devices.

Model Analyzer, formerly known as TI edge AI cloud, is a free online service that allows for the evaluation of accelerated deep learning inference on remotely accessed (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM62A3 — 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power system, video doorbell, security camera AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, video surveillance, lawn robot AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX TDA4VM — Dual Arm® Cortex®-A72 SoC and C7x DSP with deep-learning, vision and multimedia accelerators TDA4VM-Q1 — Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning
Hardware development
Evaluation board
J721EXCPXEVM — Common processor board for Jacinto™ 7 processors J721EXSOMXEVM — TDA4VM and DRA829V socketed system on module (SoM) SK-TDA4VM — TDA4VM processor starter kit for edge AI vision systems SK-AM62A-LP — AM62A starter kit for low-power Sitara™ processors SK-AM68 — AM68x starter kit for Sitara™ processors SK-AM69 — Starter kit for Sitara™ processors
Software
Software development kit (SDK)
PROCESSOR-SDK-AM62A — Software development kit for AM62A Sitara™ processors for edge AI applications
Support software
PROCESSOR-SDK-AM68A — Software development kit for AM68A processors PROCESSOR-SDK-AM69A — Software development kit for AM69A processors
Launch
Package Pins Download
FCBGA (ALY) 1414 View options
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