Product details

Architecture FET / CMOS Input, Fixed Gain/Buffer Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 9 Total supply voltage (Max) (+5V=5, +/-5V=10) 13 GBW (Typ) (MHz) 3100 BW @ Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (Typ) (V/us) 7000 Vn at flatband (Typ) (nV/rtHz) 2.3 Vn at 1 kHz (Typ) (nV/rtHz) 10 Iq per channel (Typ) (mA) 34 Vos (offset voltage @ 25 C) (Max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (C) -40 to 85 Input bias current (Max) (pA) 25 Offset drift (Typ) (uV/C) 700 Output current (Typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
Architecture FET / CMOS Input, Fixed Gain/Buffer Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 9 Total supply voltage (Max) (+5V=5, +/-5V=10) 13 GBW (Typ) (MHz) 3100 BW @ Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (Typ) (V/us) 7000 Vn at flatband (Typ) (nV/rtHz) 2.3 Vn at 1 kHz (Typ) (nV/rtHz) 10 Iq per channel (Typ) (mA) 34 Vos (offset voltage @ 25 C) (Max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (C) -40 to 85 Input bias current (Max) (pA) 25 Offset drift (Typ) (uV/C) 700 Output current (Typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
VQFN (RGT) 16 9 mm² 3 x 3
  • Large-signal bandwidth (1 VPP): 3.1 GHz
  • Slew rate: 7000 V/µs
  • Input voltage noise: 2.3 nV/√Hz
  • 1% settling time: 0.7 ns
  • Input-impedance: 50 GΩ || 2.4 pF
  • Capable of driving 50 Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5 V to ±6.5 V
  • Large-signal bandwidth (1 VPP): 3.1 GHz
  • Slew rate: 7000 V/µs
  • Input voltage noise: 2.3 nV/√Hz
  • 1% settling time: 0.7 ns
  • Input-impedance: 50 GΩ || 2.4 pF
  • Capable of driving 50 Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5 V to ±6.5 V

The BUF802 device is an open-loop, unity gain buffer with a JFET-input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front-ends. The BUF802 supports DC to 3.1 GHz of bandwidth while offering excellent distortion and noise performance across the frequency range.

The BUF802 may be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses an innovative architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin, which enables designers to trade bandwidth and distortion for a lower quiescent current, thus making the part suitable across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and its subsequent signal-chain from overdrive voltages.

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The BUF802 device is an open-loop, unity gain buffer with a JFET-input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front-ends. The BUF802 supports DC to 3.1 GHz of bandwidth while offering excellent distortion and noise performance across the frequency range.

The BUF802 may be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses an innovative architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin, which enables designers to trade bandwidth and distortion for a lower quiescent current, thus making the part suitable across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and its subsequent signal-chain from overdrive voltages.

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Technical documentation

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Type Title Date
* Data sheet BUF802 Wide-Bandwidth, 2.3 nV/√Hz, High-Input Impedance Buffer datasheet (Rev. C) PDF | HTML 18 Mar 2022
Application note How to Tune the S-Parameters of Your Analog Front-End Signal Chain PDF | HTML 25 Feb 2022
EVM User's guide BUF802RGTEVM User's Guide (Rev. A) PDF | HTML 04 Feb 2022
Technical article Achieving high-DC precision and wide large signal bandwidth with Hi-Z buffers 18 Jan 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

BUF802RGTEVM — BUF802 evaluation module high-speed, wide-bandwidth, 2.3-nV/√Hz, input buffer in RGT package

The BUF802RGTEVM is designed to easily demonstrate the functionality and versatility of the buffer. The EVM features two separate circuit configurations: a composite loop with a precision amplifier and a standalone BUF802 circuit. It can be used with split or single supplies, and includes SMA (...)
User guide: PDF | HTML
Not available on TI.com
Simulation model

BUF802 PSpice model

SBOMC43.ZIP (187 KB) - PSpice Model
Simulation model

BUF802 TINA-TI Reference Circuit (Rev. D)

SBOMBQ8D.TSC (5895 KB) - TINA-TI Spice Model
Calculation tool

ANALOG-ENGINEER-CALC — Analog engineer's calculator

The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
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Calculation tool

VOLT-DIVIDER-CALC — Voltage Divider Determines A Set of Resistors for a Voltage Divider

VOLT-DIVIDER-CALC quickly determines a set of resistors for a voltage divider. This KnowledgeBase Javascript utility can be used to find a set of resistors for a voltage divider to achieve the desired output voltage. This calculator can also be used to design non-inverting attentuation circuits.

(...)

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
VQFN (RGT) 16 View options

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