CD4011UB CMOS Quad 2-Input NAND Gate | TI.com

CD4011UB
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CMOS Quad 2-Input NAND Gate

CMOS Quad 2-Input NAND Gate - CD4011UB
Datasheet
 

Description

CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates.

The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Features

  • Propagation delay time = 30 ns (typ). at CL = 50 pF, VDD = 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Rating Data rate (Max) (Mbps) Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
CD4011UB Order now CD4000     3     18     4     2     6.8     -6.8     Standard CMOS     Push-Pull     High Speed (tpd 10-50ns)     Catalog     8     -55 to 125     14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)    
PDIP | 14
SOIC | 14
SO | 14
TSSOP | 14