CMOS Quad D-Type Flip-Flop

CD40175B-MIL

ACTIVE

Product details

Number of channels (#) 4 Technology Family CD4000 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 14 IOL (Max) (mA) 6.8 IOH (Max) (mA) -6.8 ICC (Max) (uA) 600 Features Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode
Number of channels (#) 4 Technology Family CD4000 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 14 IOL (Max) (mA) 6.8 IOH (Max) (mA) -6.8 ICC (Max) (uA) 600 Features Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode
CDIP (J) 16 135 mm² 19.65 x 6.92
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Output compatible with two HTL loads, two low power TTL loads, or one low power Schottky TTL load
  • Functional equivalent to TTL74175
  • Standardized, symmetrical output characteristics
  • Applications:
    • Shift registers
    • Buffer/storage registers
    • Pattern generators

  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Output compatible with two HTL loads, two low power TTL loads, or one low power Schottky TTL load
  • Functional equivalent to TTL74175
  • Standardized, symmetrical output characteristics
  • Applications:
    • Shift registers
    • Buffer/storage registers
    • Pattern generators

Cd40175B consists of four identical D-type flip-flops. Each flip-flop has an independent DATA D input and complementary Q and Q\ outputs. The CLOCK and CLEAR inputs are common to all flip-flops. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All four flip-flops are simultaneously reset by a low level on the CLEAR input.

These devices can function as shift register elements or as T-type flip-flops for toggle and counter applications.

The CD40175B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Cd40175B consists of four identical D-type flip-flops. Each flip-flop has an independent DATA D input and complementary Q and Q\ outputs. The CLOCK and CLEAR inputs are common to all flip-flops. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All four flip-flops are simultaneously reset by a low level on the CLEAR input.

These devices can function as shift register elements or as T-type flip-flops for toggle and counter applications.

The CD40175B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 9
Type Title Date
* Data sheet CD40175B TYPES datasheet (Rev. C) 13 Oct 2003
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins Download
CDIP (J) 16 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos