Product details

Number of channels (#) 2 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Technology Family CD4000 Input type Standard CMOS Output type Push-Pull ICC (uA) 600 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Features Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode, Retriggerable
Number of channels (#) 2 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Technology Family CD4000 Input type Standard CMOS Output type Push-Pull ICC (uA) 600 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Features Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode, Retriggerable
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5
  • Retriggerable/resettable capability
  • Trigger and reset propagation delays independent of RX, CX
  • Triggering from leading or trailing edge
  • Q and Q\ buffered outputs available
  • Separate resets
  • Wide range of output-pulse widths
  • 100% tested for maximum quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices."
  • Applications:
    • Pulse delay and timing
    • Pulse shaping
    • Astable multivibrator

  • Retriggerable/resettable capability
  • Trigger and reset propagation delays independent of RX, CX
  • Triggering from leading or trailing edge
  • Q and Q\ buffered outputs available
  • Separate resets
  • Wide range of output-pulse widths
  • 100% tested for maximum quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices."
  • Applications:
    • Pulse delay and timing
    • Pulse shaping
    • Astable multivibrator

CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.

An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RX and CX.

Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.

In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.

The time period (T) for this multivibrator can be approximated by: TX= ½ RXCX for CX 0.01 uF. Time periods as a function of RX for values of CX and VDD are given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.

The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CX for values of RX and VDD.

The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.

For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.

These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

The CD4098B is similar to type MC14528.

CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.

An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RX and CX.

Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.

In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.

The time period (T) for this multivibrator can be approximated by: TX= ½ RXCX for CX 0.01 uF. Time periods as a function of RX for values of CX and VDD are given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.

The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CX for values of RX and VDD.

The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.

For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.

These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

The CD4098B is similar to type MC14528.

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Technical documentation

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Type Title Date
* Data sheet CD4098B Types datasheet (Rev. C) 29 Oct 2004
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) 13 Mar 2020
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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PDIP (N) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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