Product details

Technology Family AC Supply voltage (Min) (V) 1.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 80 Input type Standard CMOS Output type Open-Drain Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
Technology Family AC Supply voltage (Min) (V) 1.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 6 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 80 Input type Standard CMOS Output type Open-Drain Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

The ’AC05 devices contain six independent inverters. These devices perform the Boolean function Y = A\. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.

The ’AC05 devices contain six independent inverters. These devices perform the Boolean function Y = A\. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.

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Technical documentation

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Type Title Date
* Data sheet Hex Inverters With Open-Drain Outputs datasheet (Rev. C) 12 Jun 2002
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Simulation model

CD74AC05 Behavioral SPICE Model CD74AC05 Behavioral SPICE Model

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

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