CD74ACT02

Name: CD74ACT02
Brand: TI
SKU: CD74ACT02
Price: .243 USD

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4-ch, 2-input, 4.5-V to 5.5-V NOR gates with TTL-compatible CMOS inputs

Data sheet

Quadruple 2-Input Positive-NOR Gates datasheet (Rev. B)

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4-ch, 2-input, 4.5-V to 5.5-V NOR gates with TTL-compatible CMOS inputs

CD74ACT02

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Data sheet

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Product details

Parameters

Technology Family

ACT

Number of channels (#)

Supply voltage (Min) (V)

4.5

Supply voltage (Max) (V)

5.5

Inputs per channel

IOL (Max) (mA)

IOH (Max) (mA)

-24

Output type

Push-Pull

Input type

TTL-Compatible CMOS

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (Max) (Mbps)

Rating

Catalog

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Package | Pins | Size

PDIP (N)

181 mm² 19.3 x 9.4

SOIC (D)

52 mm² 8.65 x 6

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Features

Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

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Description

The ’ACT02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A\ • B\ or Y = (A + B)\ in positive logic.

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Technical documentation

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	Type	Title	Date
*	Data sheet	Quadruple 2-Input Positive-NOR Gates datasheet (Rev. B)	Jun. 12, 2002
	Technical article	How to keep your motor running safely	Jun. 04, 2020
	Selection guide	Logic Guide (Rev. AB)	Jun. 12, 2017
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. D)	Jun. 23, 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	Dec. 02, 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	Jan. 16, 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	Jul. 08, 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	Jun. 22, 2004
	More literature	Logic Cross-Reference (Rev. A)	Oct. 07, 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	Aug. 29, 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	Jun. 01, 1997
	Application note	Designing With Logic (Rev. C)	Jun. 01, 1997
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	Apr. 01, 1996