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Technology Family HC Function Digital Multiplexer Configuration 8:1 Number of channels (#) 1 Operating temperature range (C) -55 to 125 Rating Catalog
Technology Family HC Function Digital Multiplexer Configuration 8:1 Number of channels (#) 1 Operating temperature range (C) -55 to 125 Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4
  • HC/HCT354
    • Transparent Data and Select Latches
  • Buffered Inputs
  • Three-State Complementary Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25°C
    • Data to Output = 18ns
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

  • HC/HCT354
    • Transparent Data and Select Latches
  • Buffered Inputs
  • Three-State Complementary Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25°C
    • Data to Output = 18ns
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE\.

In the HC/HCT354 the data enable input, E\, controls transparent latches that pass data to the outputs when E\ is high and latches in new data when E\ is low.

In both types the three-state outputs are controlled by three output-enable inputs OE1\, OE2\, and OE3.

The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE\.

In the HC/HCT354 the data enable input, E\, controls transparent latches that pass data to the outputs when E\ is high and latches in new data when E\ is low.

In both types the three-state outputs are controlled by three output-enable inputs OE1\, OE2\, and OE3.

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Technical documentation

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Type Title Date
* Data sheet CD54HC354, CD74HC354, CD74HCT354 datasheet (Rev. D) 07 Apr 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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