Product details

Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 6 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 160 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 6 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 160 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6
  • Buffered Inputs
  • High Current Bus Driver Outputs
  • Two Independent Three-State Enable Controls
  • Typical Propagation Delay tPLH,tPHL = 8ns at VCC =5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, I1 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

  • Buffered Inputs
  • High Current Bus Driver Outputs
  • Two Independent Three-State Enable Controls
  • Typical Propagation Delay tPLH,tPHL = 8ns at VCC =5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, I1 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs.

The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting buffers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls the remaining 2 gates.

The ’HCT367 and CD74HCT368 logic families are speed, function and pin compatible with the standard LS logic family.

The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs.

The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting buffers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls the remaining 2 gates.

The ’HCT367 and CD74HCT368 logic families are speed, function and pin compatible with the standard LS logic family.

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Technical documentation

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Type Title Date
* Data sheet CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 datasheet (Rev. D) 16 Oct 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

CD74HC368 Behavioral SPICE Model

SCHM084.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

Ordering & quality

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