CD74HC4066

ACTIVE

12-V, 1:1 (SPST), (SPST), 4-channel analog switch

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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 12, 2.5, 3.3, 5 Ron (Typ) (Ohms) 15 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (C) -55 to 125 Input/output continuous current (Max) (mA) 25 Rating Catalog CON (Typ) (pF) 5 open-in-new Find other Analog switches & muxes

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Analog switches & muxes

Features

  • Wide Analog-Input-Voltage Range . . . . 0V - 10V
  • Low "ON" Resistance
    • VCC = 4.5V . . . . . . . .25
    • VCC = 9V . . . . . . . .15
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V and 10V
  • HCT Types
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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Description

The ’HC4066 and CD74HCT4066 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear "ON" resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input.

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Technical documentation

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Type Title Date
* Data sheet CD54HC4066, CD74HC4066, CD74HCT4066 datasheet (Rev. D) Aug. 21, 2003
Application note Selecting the Right Texas Instruments Signal Switch (Rev. C) Aug. 06, 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Application note Multiplexers and Signal Switches Glossary (Rev. A) Jun. 09, 2021
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

INTERFACE ADAPTER Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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