CDC351

ACTIVE

1-line to 10-line 3.3-V clock driver with tri-state outputs

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Product details

Parameters

Function Single-ended Output frequency (Max) (MHz) 100 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 0.6 Features Pin control Operating temperature range (C) -40 to 85, 0 to 70 Rating Catalog Output type LVTTL Input type LVTTL open-in-new Find other Clock buffers

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 SSOP (DB) 24 64 mm² 8.2 x 7.8 open-in-new Find other Clock buffers

Features

  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to Ten Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-32-mA IOH, 32-mA IOL)
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

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Description

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

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Technical documentation

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* Data sheet 1-Line To 10-Line Clock Driver With 3-State Outputs datasheet (Rev. D) Jun. 17, 2003

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CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options
SSOP (DB) 24 View options

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