CDCLVP1216

ACTIVE

Low Jitter, 2-Input Selectable 1:16 Universal-to-LVPECL Buffer

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Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 57 Output frequency (Max) (MHz) 2000 Number of outputs 16 VCC out (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 2:16 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock buffers

Features

  • 2:16 Differential Buffer
  • Selectable Clock Inputs Through Control Pin
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/
    LVTTL
  • 16 LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 110 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz to
    20-MHz Offset Range:
    • 57 fs, RMS (Typical) at 122.88 MHz
    • 48 fs, RMS (Typical) at 156.25 MHz
    • 30 fs, RMS (Typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 550 ps
  • Maximum Output Skew: 30 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a
    Thermal Pad)
  • ESD Protection Exceeds 2000 V (HBM)
  • Available in 7-mm × 7-mm VQFN-48 (RGZ) Package
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Description

The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from –40°C to +85°C.

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LMK00301 ACTIVE 3-GHz, 10-Output Differential Fanout Buffer / Level Translator Ultra low additive jitter,1:10 Universal Differential Buffer that can support LVPECL

Technical documentation

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Type Title Date
* Datasheet CDCLVP1216 16-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) Dec. 07, 2015
User guides CDCLVP1216EVM User's Guide May 27, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$149.00
Description

CDCLVP1216EVM is the evaluation module for CDCLVP1216. The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs. It has a maximum clock frequency up to 2 GHz. The overall additive (...)

Features
  • 2:16 LVPECL Differential Buffer
  • Selectable Clock Inputs Through Control Pin
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 110mA
  • Very Low Additive Jitter: < 100 fs,rms in 10 kHz to 20 MHz Offset Range
  • 2.375 V to 3.6 V Device Power (...)

Design tools & simulation

SIMULATION MODELS Download
SLLM056B.ZIP (40 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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