Product details

Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3, 2.5, 1.8 Output supply voltage (V) 3.3, 2.5, 1.8 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3, 2.5, 1.8 Output supply voltage (V) 3.3, 2.5, 1.8 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7
  • Superior Performance With Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms Typical Jitter)
    • 0.5-W Typical Power Consumption
    • High Channel-to-Channel Isolation and Excellent PSRR
    • Device Performance Customizable Through Flexible 1.8-V, 2.5-V and 3.3-V Power Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-Divided Differential Clock Outputs Supporting LVPECL-Like, CML, or LVDS-Like Signaling
    • 4x Fractional or Integer Divided Differential Clock Outputs Supporting HCSL, LVDS-Like Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1 ppm Frequency Error and Eliminates Need for Crystal Oscillators and Other Clock Generators
    • Output Frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for Smart Switching
  • SPI, I2C, and Pin Programmable
  • Professional User GUI for Quick Design Turnaround
  • 7 × 7 mm 48-VQFN package (RGZ)
  • –40°C to 85°C Temperature Range
  • Superior Performance With Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms Typical Jitter)
    • 0.5-W Typical Power Consumption
    • High Channel-to-Channel Isolation and Excellent PSRR
    • Device Performance Customizable Through Flexible 1.8-V, 2.5-V and 3.3-V Power Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-Divided Differential Clock Outputs Supporting LVPECL-Like, CML, or LVDS-Like Signaling
    • 4x Fractional or Integer Divided Differential Clock Outputs Supporting HCSL, LVDS-Like Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1 ppm Frequency Error and Eliminates Need for Crystal Oscillators and Other Clock Generators
    • Output Frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for Smart Switching
  • SPI, I2C, and Pin Programmable
  • Professional User GUI for Quick Design Turnaround
  • 7 × 7 mm 48-VQFN package (RGZ)
  • –40°C to 85°C Temperature Range

The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, Small Cells, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208 also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208 can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, Small Cells, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208 also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208 can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

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Technical documentation

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Type Title Date
* Data sheet CDCM6208 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers datasheet (Rev. G) 09 Jan 2018
Application note How to measure Total Jitter (TJ) (Rev. B) 08 Aug 2017
Technical article The five benefits of multifaceted clocking devices 17 May 2016
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Timing is Everything: Understanding LVPECL and a newer LVPECL-like output driver 09 Jan 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Application note Crystal or Crystal Oscillator Replacement with Silicon Devices 18 Jun 2014
User guide CDCM6208 EVM User's Guide (Rev. A) 19 Dec 2012
Application note Driving the TLK10002 10Gpbs SERDES with the CDCM6208 Clock Generator 14 Dec 2012
Application note A Step by Step Guide on Using the MSP430 as a Bootloader for the CDCM6208VxEVM (Rev. A) 04 Dec 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCM6208V1EVM — CDCM6208V1 Evaluation Module

The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML (...)

In stock
Limit: 2
Evaluation board

CDCM6208V2EVM — CDCM6208V2 Evaluation Module

The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML (...)

In stock
Limit: 2
Development kit

EVMK2G — 66AK2Gx (K2G) Evaluation Module

The K2G Evaluation Module (EVM) enables developers to immediately start evaluating the 66AK2Gx - 600MHz processor, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive applications.  Similar to (...)

In stock
Limit: 5
Development kit

EVMK2GX — 66AK2Gx 1GHz evaluation module

The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

In stock
Limit: 3
Development kit

EVMK2GXS — 66AK2Gx (K2G) 1GHz High-Secure Evaluation Module

The K2G 1GHz High Secure Evaluation Module (EVM) enables developers to start  evaluating and testing the programming of the  high secure developmental version of the  66AK2Gx processor, and to accelerate the next stage of secure boot product development of audio and industrial real (...)

GUI for evaluation module (EVM)

CDCM6208 EVM Control GUI (Rev. D)

SCAC134D.ZIP (2469 KB)
Simulation model

CDCM6208 IBIS Model

SCAM058.ZIP (241 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDEP0069 — 66AK2Gx DSP + ARM Processor Audio Processing Reference Design

This reference design is a reference platform based on the 66AK2Gx DSP + ARM processor  System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software (...)
Reference designs

TIDEP0067 — 66AK2Gx DSP + ARM Processor Power Solution Reference Design

This reference design is  based on the 66AK2Gx multicore System-on-Chip (SoC) processor and companion TPS65911 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2Gx processor in a single device. This power solution design also includes the (...)
Reference designs

TIDEP0068 — PCI Express PCB Design Considerations Reference Design for the K2G General Purpose EVM (GP EVM)

PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2Gx DSP + ARM Processor system on chip (SoC).  This PCIe PCB design considerations reference design  (...)
Reference designs

TIDEP0070 — DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-based Systems

This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC).  It enables developers to implement a high (...)
Reference designs

TIDA-00352 — SDI Video Aggregation Reference Design

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
Reference designs

TIDA-00309 — DisplayPort Video 4:1 Aggregation Reference Design

This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
Reference designs

TIDA-00269 — Gigabit Ethernet link aggregator reference design

The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
Reference designs

TIDA-00234 — Dual-channel XAUI to SFI reference design for systems with two or more SFP+ optical ports

The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
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